The GILES Research Project:
Automatic Layout of FPGAs from an Architectural Specification.


One of the most difficult and time-consuming steps in the creation of the FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this project we have built a new CAD system that automatically generates a transistor-level schematic from a high-level architectural specification of an FPGA tile. It is called GILES, for Good Instant Layout of Erasable Semiconductors. It also generates a cell-level netlist that is placed and routed in a fully automatic manner. The architectural specification is the one used as input to the VPR architectural exploration tool. The output is the mask-level layout of a single tile that can be replicated to form an FPGA array. It includes a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a special-purpose router built for this task. GILES can place and route a tile consisting of four 4-input LUT logic cells and all of its programmable wires in a 0.18um CMOS process using 8 layers of metal and 25983um2 of area. When we generate the layout of a reverse-engineered netlist very close to the Xilinx Virtex-E FPGA (built in a 0.18um process) GILES requires only 46% more area than the original.

TAPE OUT: See here for a picture of a 192-LUT FPGA laid out using GILES and more that was taped out to CMC on a 0.18um TSMC process in May of 2004. Here is a die photo of the chip that was manufactured. Click here for a report on the testing of the chip received in November, 2004.

Here is a paper describing the Powell chip design in detail and more recent results on the comparison between automated layout area and commercial hand-tuned layout:
I. Kuon, A. Egier and J. Rose, "Design, Layout and Verification of an FPGA using Automated Tools" in FPGA '05, ACM Symposium on FPGAs, February 2005, pp 215-226.

Here is a paper describing the GILES tool and preliminary results:

K. Padalia, R. Fung, M. Bourgeault, A. Egier and J. Rose, "Automatic Transistor and Physical Design of FPGA Tiles From An Architectural Specification" in FPGA 2003, ACM Symp. FPGAs, Feburary 2003, pp. 164-172. (PDF) .

Here are the Master's theses, Bachelor's Tesis and Bachelor's design project that produced these results:

Automated FPGA Design, Verification and Layout, Ian Kuon, M.A.Sc. Thesis, University of Toronto, 2004.

Enhancing and Using an Automatic Design System for Creating FPGAs, Aaron Egier M.A.Sc. Thesis, University of Toronto, 2004.

Automatic Transistor-Level Design and Layout Placement of FPGA Logic and Routing from an Architectural Specification, - Ketan Padalia, University of Toronto Engineering Science Bachelor's Thesis, May 2001

Optimization Of Transistor-Level Floorplans For Field-Programmable Gate Arrays - Ryan Fung, University of Toronto Engineering Science Bachelor's Thesis, May 2002

Automatic Transistor-Level Design and Layout of FPGAs - Mark Bourgeault, Joshua Slavkin and Chris Sun, University of Toronto, Department of Electrical and Computer Engineering Design Project Final Report, May 2002

Automating Transistor Resizing in the Design of Field-Programmable Gate Arrays Anthony Chan, University of Toronto Engineering Science Bachelor's Thesis, May 2003

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