Andreas Moshovos
Associate Professor
Computer Engineering Group
Engineering Annex 311 (map)
Department of Electrical and Computer Engineering
Department of Computer Science (courtesy)
University of Toronto
moshovos@eecg.toronto.edu
416-946-7373
FAX: 416-946-8734

 

 

 [Research][Group Members][Courses][Publications][Committees][Education][Nikos Moshovos]

 

Micro-Architecture Group / Research Interests

The AENAO group is addressing emerging challenges in digital system design with an emphasis on power, complexity and performance optimizations for general purpose processors. Our research has produced several key innovations, including:

 

  • Power-Aware Snoop Coherence Filters: Our group was the first to draw attention to the opportunities and the need for power optimizations for cache coherence mechanisms. We proposed Jetty, a simple, layered extension over snoop coherence that stops remotely-induced snoops from accessing the local cache tag arrays, thus saving power and reducing bandwidth on the tag arrays. In Jetty we also introduced hardware counting bloom-like filters a structure that provides fast and power efficient membership tests. Other researchers since then have used similar structures for other optimizations such as load/store queue complexity reduction and hit/miss prediction. Recently, we proposed a novel implementation of these filters that further improves their power and speed. In more recent work, our group introduced RegionScout a technique that avoids broadcasts in snoop-coherent systems. RegionScout improves upon Jetty in that the source node knows a priori that a request will miss in all other nodes. Jetty has influenced the design of commercial snoop filters.
  • Checkpoint Prediction and Intelligent Management: Our group was the first to draw attention to the lack of scalability in existing checkpoint/restore mechanisms that are used to support speculation in modern processors. We proposed checkpoint prediction along with intelligent checkpoint management methods to sustain high-performance with much fewer checkpoints.
  • Memory Dependence Prediction: In our earlier work while at the University of Wisconsin-Madison, we proposed a novel solution the the decades old problem of memory aliasing. Memory dependence prediction dynamically predicts dependences amongst memory operations. We proposed several optimizations. Some of these optimizations have been since implemented in commercial designs, including the latest microarchitecture from Intel Corporation.

Our research currently focuses on two important design challenges: (i) the ever-growing gap between processor and memory performance, and (ii) the increasing complexity and reduced reliability of existing performance enhancing techniques coupled with the prohibitive levels of power dissipation. In addition, our research also considers how the enhanced semiconductor technologies can be used to enhance functionality. Our research focuses primarily in developing techniques for addressing perceived, long-term design challenges. A common theme amongst the techniques that we develop is that they are behavior-centric (i.e., they exploit aspects of the behavior of "typical" applications), programmer transparent (they required no changes to existing software) and often layered extensions (i.e., they can be incorporated into existing designs with minimal changes).

Talk on Recent Research Results given at several places including: IBM T.J. Watson, UIUC, Northwestern, Intel Oregon and Santa Clara, EPFL, and CMU.

We thank www.virtutech.com for their continuing support through an academic license for SimICS.

 

Group Members

 

Alumni

    • Amirali Baniasadi, Faculty at the University of Victoria.
    • Gaurav Mittal, M.Sc. Dec. 2001.
    • Christopher Thomas
    • Won-Ho Park
    • Navid Azizi, Co-Advised w/ Prof. Farid Najm
    • Patrick Akl  currenly with AMD/ATI

 

 

Courses

 
    • Topics in Modern Computer Architecture: Performance, Reliability, Power and Functionality: Fall 2008.
    • Computer Organization: Fall 2001 Offering, Winter 2005, Winter 2006, Winter 2007, Winter 2008.
    • Digital and Computer Systems: Fall 2001 Offering Also given in Fall '00
    • Advanced Computer Architecture: 02. 05, 06, 07.
    • Introduction to Digital Design Winter '99 and Fall '99 (ECE B01 Northwestern Univ.)
    • Advanced Computer Architecture, Spring '99 and '00 (ECE D52, Northwestern Univ.)
    • Advanced Parallel Computer Architecture, Winter '00 (ECE D53, Northwestern Univ.)

 

Publications

 

Please respect all applicable copyrights. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage. To copy otherwise, or to republish requires a fee and/or specific permission of the ACM/IEEE

 

2008

 

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1992

Implementing Non-Numerical Algorithms On An Access Decoupled Architecture That Supports Software Pipelining
Andreas Moshovos,Advisor: M. Katevenis.
M.Sc. Thesis, Aug. 1992.

 

Technical Program Committees

 
  • Fourth Conference on High-Performance Embedded Architectures and Compilers  (HiPEAC), 2009.
  • 12th Pan-Hellenic Conference on Informatics (PCI 2008)
  • International Conference on Computer Design (ICCD), 2008.
  • Design and Automation Europe (DATE), 2008.
  • SAMOS Workshop, 2008.
  • International Conference on Parallel Processing, 2008
  • IEEE Intl. Symposium on High-Performance Computer Architecture (HPCA), 2008.
  • Third Conference on High-Performance Embedded Architectures and Compilers  (HiPEAC), 2008.
  • Design and Automation Europe (DATE), 2007.
  • ACM/IEEE Conference on Parallel Architectures and Compilation Techniques (PACT), 2007.
  • ACM/IEEE Intl. Symposium on Microarchitecture (MICRO), 2007.
  • ACM/IEEE Intl. Symposium on Computer Architecture (ISCA), 2007.
  • IEEE International Parallel & Distributed Processing Symposium (IPDPS), March 2007.
  • ACM Annual International Conference on Supercomputing, July 2006.
  • Second International Workshop on Data Management on New Hardware (DaMoN), June 2006.
  • Workshop on Architectural Support for Gigascale Integration (ASGI), June 2006.
  • ACM/IEEE Intl. Symposium on Microarchitecture (MICRO), Nov. 2005.
  • First HiPEAC Conference, 2005.
  • Intl. Conference on Parallel Processing (ICPP), June 2005.
  • Workshop on Power-Aware Computer Systems, 2004
  • IEEE Symposium on the Performance Analysis of Systems and Software, ISPASS 2001
  • 4th International Symposium on High Performance Computing, (ISHPC-IV), 2002.
  • Sub-chair on Architecture, Intl. Conference on Parallel Processing, 2002.
  • Workshop on Power-Aware Computer Systems, 2001.
  • Workshop on Power-Aware Computer Systems 2000.

 

Education