Using your best RTL HDL coding style, write a Verilog or VHDL program that implements the following function:
The input, call it WORDIN, receives a stream of 21 parallel data bits. Defining the bits starting from the MSB:
The MSB indicates whether the word is Instruction/Data. It is set to 1 if it is an instruction, 0 if data.
Data Word Format
The data word represents .
Instruction Word Format
The task is to sum all of the input data words, accounting for the scaling factors. The start of a new set of data is a START instruction ended by a STOP instruction. Any NOP instructions are to be ignored. You should check that the number of data words received up to the STOP instruction matches the number given in the START instruction.
There is also a CLK input. WORDIN is valid at the rising edge of CLK.
The main output is called SUMOUT, which is 28 bits long. SUMOUT shows the last valid SUM.
The VALIDSUM output bit is an output that is high for one clock cycle when SUMOUT is changed.
If an error has occurred, like an illegal instruction, there is an output, called ERROR, that should be set high until the next valid SUM is generated.
if an overflow has occurred, the OVR output should be set high until the next valid SUM is generated.
What to do