The "FPGA Place-and-Route Challenge"

Current best routing track total: 177 tracks.

To encourage FPGA researchers to benchmark their CAD tools on large circuits, we have created an "FPGA Place-and-Route Challenge." For every track by which a researcher reduces the total number of tracks required to route these circuits (from the previously best total number of 177) we will pay him/her $1! (Sorry, $1 Cdn, not $1 U.S.)

The number of tracks in a routing channel is simply the number of wires that may be used in that channel (i.e. the "width" of the channel). The total number of tracks required to route the 20 benchmark circuits is simply the sum over all 20 circuits of the minimum channel width required to successfully route each circuit.

Current and Historical Champions

The current lowest track count (total 177 tracks) is VPR version 4.30, with the following options:

-place_algorithm bounding_box -max_router_iterations 100 -pres_fac_mult 1.5 -router_algorithm breadth_first

This makes VPR use its wirelength-driven placement and routing algorithm, and makes the router work somewhat harder than usual. The sum of the track count needed to route each circuit is 177 tracks. The CPU times are still quite reasonable; the time to place and repeatedly route each circuit averages about 3 hours on a fairly obselete 300 MHz Ultrasparc processor.

Past record holders are the combination of VPR to place a circuit and SC-Pathfinder to route the circuit (total 188 tracks) and VPR version 3.99 with default placement and routing effort (total 194 tracks).

The FPGA Architecture

Click here to see all the details of the FPGA architecture your tools must target. Read these rules carefully and make sure your tools are targetting the architecture exactly! Otherwise, your results won't be comparable to those of other researchers and we won't be able to accept them.

If you want to run VPR on this architecture, click here to get the .arch file describing this architecture in VPR format.

The Benchmark Circuits

Press the green button to download the specified item.

Download the .net format netlists of the twenty large MCNC circuits used as benchmarks for the place-and-route challenge.

Download the placements produced by VPR 4.30, wirelength-driven placement algorithm with default effort, for the twenty large circuits above. (You only need these placements if your CAD tool does only routing, rather than both placement and routing.)

Click here to read a description of the circuit netlist format and the placement file format.

Other Documentation, Rules, and Reporting Results

Click here to download a paper which describes in detail the FPGA architecture you must target when placing and routing these circuits (see Section 5 of the paper).

To send in valid results for the challenge, you must:

Mail us to report a new best routing track total or if you have any questions about the challenge.


The table below shows the size of the 20 benchmark circuits, in terms of a 4-LUT + flip flop logic block, and the number of tracks required to successfully place and route each by CAD tools for which we have results.

Benchmark circuits and track counts
CircuitSize (Logic Blocks)VPR 3.99 TracksSEGA Tracks*SC-Pathfinder Tracks**VPR 4.30 Tracks***
*SEGA performs detailed routing only, so VPR was used to place and globally route the circuits. SEGA was then used for detailed routing.

**SC-Pathfinder is a routing tool only, so VPR was used to generate the placement for each circuit. SC-Pathfinder was then used to perform a combined global-detailed routing.

***VPR 4.30 run in wirelength-driven mode for placement and routing, with increased routing effort. Command line: -place_algorithm bounding_box -max_router_iterations 100 -pres_fac_mult 1.5 -router_algorithm breadth_first

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