Modern servers must provide high-performance, a requirement that is increasingly at odds with maintaing power dissipation within acceptable operational limits. Moreover, modern servers must be reliable which is becoming increasingly harder to satisfy as a result of increased power dissipation. In the AENAO project, we are investigating power-aware architectural and circuit level techniques targeted at modern and next generation server systems. We are particularly interested in the synergy of architecture and circuit design to maximize power, performance and reliability benefits. Servers and their respective workloads present unique challenges and opportunities for power optimizations. Our goal is to develop techniques that will facilitate further increases in performance while maintaining low power dissipation and non-stop operation.

AENAO:  Non-stop, perpetual in Greek. Pronounced "a-eh-n-a-oh" as in "apple,error,no,apple,odd".

Why is power important?  Existing systems have been designed to maximize performance while taking cost and complexity into account. Power dissipation, for the most part, has been ignored and for a good reason: power dissipation in previous generations has stayed within acceptable limits. As we move towards submicron technologies and multi-GHz frequencies, however, power dissipation exceeds acceptable limits jeopardizing performance and reliability. Overall power dissipation is also an important consideration for server farms where a large number of servers operate in a small space. Power delivery and dissipation become problematic and expensive.

Why servers?  The symmetric multiprocessor (SMP) is the most popular architecture for small- to medium-scale commercial computing servers: SMPs are widely used as the backbone computing platforms that support most critical modern computing services such as file, database and web servers. Moreover, SMPs are often used as the building blocks for modern superscomputers facilitating scientific experiments not previously possible. SMPs are also becoming popular as desktop/workstation platforms as they are more cost effective compared to single-processor alternatives. Finally, with the increasing levels of chip integration, SMP is also emerging as the architecture of choice for single chip/module multiprocessors.

Why Power-Aware Servers?  The wide adoption of SMPs is primarily the result of a consistent performance growth and of a consistent reduction in cost. Unfortunately, while performance and cost have been improving, the amount of power dissipated by typical SMPs has also been increasing rapidly. With the current technological projections it is simply impossible to maintain the current performance/power/cost growth trend. Unless power reduction techniques are developed, power will become the limiting factor in high-performance server designs impacting performance and cost.

Target Areas:

• We have developed preliminary energy-efficient filters (JETTY) that eliminate a variety of cache lookups for snoop-based servers.
• We are looking into extensions of these energy-efficient filters to cover various other cache and interconnect transactions for both snoop and directory-based servers.
• Furthermore, we are investigating methods that maintain competitive cache hit rates while reducing the amount of physical resources used during particular cache transactions
• Finaly, we are developing novel storage cells that maintain high performance and density while reducing leakage power. Such cells are essential for future high-performance, high-density caches.