Abstract
This talk will describe and evaluate a framework for modeling macroscopic program behavior that is applied to optimizing "prescient instruction prefetch". Prescient instruction prefetch is a novel technique for using so-called "helper threads" to improve single-threaded application performance by performing judicious and timely instruction prefetch. The framework is potentially applicable to other thread speculation techniques.
Background: A helper thread is a very small chunk of code (10's-100's of instructions) that typically performs work beneficial only due to its microarchitectural side-effects on an application's main thread. Helper threads are motivated by the trend towards increased pipeline depths and CPU-memory cycle latencies as process technology feature sizes continue to diminish. When coupled with increasingly complex yet economically important application workloads, these trends strain traditional solutions to overcoming performance bottlenecks in general purpose CPU designs.
Biography
Tor Aamodt is PhD student in the computer group supervised by Professor Paul Chow. This work was done while he interned in the microarchitecture group within Microprocessor Research, Intel Labs. This talk is a dry run for a presentation at the ACM SIGMETRICS 2003 International Conference on Measurement and Modeling of Computer Systems.