Computer Engineering Cider Seminars

This talk presents and provides an evaluation of hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using helper threads to perform instruction prefetch. Such helper threads require a means of enabling store-to-load communication and selective instruction execution when directly pre-executing future regions of an application that suffer I-cache misses. Two novel hardware mechanisms, "safe stores" and "YAT bits", are introduced that help satisfy these requirements. This talk will also present and evaluate "finite state machine recall", a technique for limiting pre-execution to branches that are hard to predict by leveraging a counted instruction prefetch mechanism. On a research Itanium SMT processor with next line and streaming I-prefetch mechanisms that incurs latencies representative of next generation processors, prescient instruction prefetch can improve performance by an average of 10.0% to 22% (depending upon memory latency) on a set of SPEC 2000 benchmarks that suffer significant I-cache misses. Prescient instruction prefetch is found to be competitive against even the most aggressive research hardware instruction prefetch technique: fetch directed instruction prefetch.

Tor M. Aamodt is a Ph.D. candidate working under the supervision of Prof. Paul Chow in the Computer Group of the Department of Electrical and Computer Engineering at the University of Toronto. From March 2002 to August 2003 he was an intern with Intel Corporation's Microarchitecture Research Lab in Santa Clara, California. He has an M.A.Sc. in computer engineering and a B.A.Sc. in engineering science from the University of Toronto.