Abstract
Technology shifts in the past several years have challenged conventional computer architectures, suggesting that bold new designs may be needed. For example, the escalation of chip-level parallelism has introduced an imbalance between computation and data access and forced decisions to be made regarding the relative importance of single-thread and multi-thread performance. Similarly, the introduction of flash memory in the design of storage devices is challenging the design of storage hierarchies and I/O intensive software. In this talk, I will survey some of these technology challenges and opportunities and discuss possible impacts on processor and system design, as well as system and application software. Coming from IBM, my focus is on computer architectures which principally support distributed enterprise software and large scale server-side processing.
Biography
Bob Blainey is a Technical Executive from the Business and Technical Strategy team in IBM's Software Group. Bob graduated from the University of Toronto in 1988 with a CS degree and joined IBM in 1989. In the early 90s, Bob had the opportunity to help launch RISC architecture systems from IBM as part of the compiler team in the Toronto lab. Bob went on to architect many key optimization infrastructures in the compilers, including work on instruction scheduling, locality optimization, interprocedural optimization and parallelization. In the early part of the past decade, Bob began to focus more on the Java programming language and virtual machine, eventually taking on the role of chief Java technologist between 2003 and 2006. Since 2006, Bob has been focused on joint work with IBM research and the IBM Systems and Technology Group in the design of new systems and software for next generation technologies such as multicore processors and solid state storage.