Abstract
A new platform for reconfigurable computing is based on an object-based programming model first, with architecture, silicon and tools designed to faithfully realize this model. The platform is aimed at application developers using software languages and methodologies, not hardware. Its objectives are massive performance, long-term scalability, and easy development.
In our structural object programming model, objects are strictly encapsulated software programs running concurrently on an asynchronous array of processors and memories. They exchange data and control through a structure of self-synchronizing asynchronous channels. Objects are combined hierarchically to create new objects, connected through the common channel interface.
The first chip is a 130nm ASIC with 336 32-bit processors, 336 2KB RAM banks with access engines, and a configurable word-wide channel interconnect. It delivers an order-of-magnitude increase in the throughput available from a programmable chip in a given silicon process. Applications written in Java and block diagrams compile in one minute. Sub-millisecond runtime reconfiguration is inherent.
Biography
Mike Butts, Ambric Fellow, is a lead hardware architect and senior technologist, with extensive experience in computer architecture and large-scale reconfigurable hardware. He co-invented FPGA-based hardware logic emulation, which spawned a market now valued at $100 million, and developed several reconfigurable chips and system products. His career was spent at companies that pioneered many fundamental electronics technologies, including Floating Point Systems, Mentor Graphics, Quickturn, Synopsys, and Cadence Design Systems, where he was named a Cadence Fellow. Prior to Ambric he was co-founder of Tabula.
Mike has 35 U.S. patents issued with additional patents worldwide and pending. A widely published author, he has served on the Technical Program Committees of the IEEE International Symposium on Field-Configurable Custom Computing Machines (FCCM); the ACM International Symposium on FPGAs; and the International Conference on Field Programmable Logic and Applications (FPL). He received his BSEE and MSEE/CS at MIT.