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This cider seminar will look at a 3D Computational RAM we taped out and functional multilevel DRAMs. There have been several recent announcements about 3D IC processes. The MIT Lincoln Labs 3D SOI process stacks ~10 micron films of transistors and interconnect, taken from back-etched wafers. Techniques were developed to allow arbitrary stacking of a single design while enhancing yield of this high-density processor-in-memory 3D Chip. Switching from spatial to electrical, the density of DRAMs can be enhanced by storing more levels per cell. This is more challenging than the commonplace multilevel ROMs and flash memories. We have ICs working with a variety of sensing techniques and numbers of levels. |