Abstract
Automatic Test Pattern Generation (ATPG) is one of the core algorithms in testing of digital circuits and systems. Test patterns are needed to check the correct function of a chip after production. For this purpose fault models are applied at the gate level to determine these test patterns. With the number of elements integrated on a chip increasing at an exponential rate, the underlying algorithms have to be steadily improved.
Due to recent advances in algorithms to solve Boolean Satisfiability (SAT), there is a renewed interest in ATPG based on SAT. While the early approaches only used two-valued logic, modern tools have to use multiple values to model unknown states and tri-state elements for buses. Moreover, structural knowledge must be embedded into the SAT problem to efficiently generate test patterns and learned information can be reused across multiple problem instances. Experimental results show that the integration of SAT-based ATPG and traditional ATPG algorithms improves the robustness of the overall tool flow.
Biography
Dr. Gorschwin Fey received his diploma in Computer Science from the Martin-Luther-Universitt in Halle, Germany in 2001. Since 2002 he is with the research group of Computer Architecture at the University of Bremen headed by Prof. Dr. Rolf Drechsler. In 2006 Dr. Fey received the doctoral degree. His research interests include formal verification, test pattern generation and the underlying algorithms and data structures.