Abstract
FPGAs are among the largest chips made, and they are the earliest adopters of new technology nodes. Plus, as transistor and wire geometries shrink, very tiny defects where were previously "ignorable" become prominent. Hence, it will soon be imperative to find ways to sell FPGA devices that contain multiple faults to recoup yield loss. This talk will explore two different ways of introducing architecture-level redundancy to tolerate multiple manufacturing defects. On the one hand, a coarse-grain approach will be presented which utilizes multiple spare rows and columns. This will be compared to a fine-grain approach which utilizes spare wires within each routing channel. The differences are clear: the coarse-grain approach works very well for tolerating only a few defects, but the fine-grain approach is capable of tolerating significantly more. What further sets the fine-grain approach apart is its ability to tolerate an increasing number of defects as the FPGA array size is increased.
Biography
Anthony has just recently finished his MASc at the University of British Columbia under the supervision of Prof. Guy Lemieux. He has experience with both Altera and Xilinx CAD tools and devices. Before starting grad school, he worked full-time at Agilent in Vancouver on their RouterTester product. The talk is based on a recent paper presented at FPL2005 and an upcoming one to appear at FPT2005.