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This is a practise session for the upcoming FPGA 2001 conference. You can find the associated paper on Guy's publications page. A recent trend in FPGA architectural design is to use a clustered architecture, where a number of lookup tables (LUTs) are grouped together to act as the configurable logic block. These LUT clusters are often fully-connected to each other like in a full crossbar. Such a high degree of connectivity makes routing easier, but has significant area overhead. In this talk we will explore the use of sparse crossbars as a switch matrix inside the clusters between the cluster inputs and the LUT inputs. By reducing the switch densities inside these matrices by 50% or more, between 10 to 18% in area can be saved with no degradation to critical-path delay. To compensate for the loss of routability, increased compute time and spare cluster inputs are required. Further investigation may yield modest area and delay reductions. Guy Lemieux is a Phd student in the Computer Engineering Group. |