Abstract
This talk will present the optimizations made for the NIOS processor when it was targeted for the APEX architecture. These optimizations resulted in a significantly smaller and faster processor. This talk will focus on the heart of the processor, the ALU. The improvements to the ALU were made in two ways: by making heavy reuse of the Logic Blocks for different instructions, and also by using special features of the APEX Logic Cells, as this talk will show.
Biography
Dr Paul Metzgen has a Masters in EE from Cambridge University, and a Masters and PhD in Computer Science from the University of Oxford. Paul has worked at Sun Microsystems in the Mountain View, Sharp European Laboratories (working on a software to hardware compiler), and is currently a Senior Member of Technical Staff at Altera. At Altera, Paul has worked on the NIOS processor, developed new RTL optimization algorithms for Quartus II, and has worked closely with a number of customers to help optimize their designs for the Altera FPGA architecture.