Abstract
This seminar will give an overview of the Stratix-II FPGA, Altera's recently announced flagship FPGA product built on a 90nm IC process technology. Its architecture includes many significant improvements, most particularly a change from the standard 4-input lookup table (LUT) logic fabric to a "fracturable" 6-input LUT that has many powerful and interesting properties. The talk will cover the research and development work that went into making these improvements, as well as give an overview of the various features in Stratix-II, including:
- High-speed I/O Signalling (1 Gbps in dedicated SERDES circuitry)
- Dynamic Phase Alignment Circuitry
- External Memory Interface circuitry (eg. DDR2 SDRAM)
- 128-bit AES bitstream encryption
- TriMatrix Memory (three kinds of on-chip memory)
- DSP Blocks (dedicated multiplier, pipeline, and accumulate circuitry)
- Clock Management Circuitry (PLLs)
- Remote Upgrades (dedicated recovery circuitry and ability to send upgrades over any network)
Biography
In 2001, Ketan Padalia completed his B.A.Sc. in the Computer option of the Engineering Science program at the University of Toronto. He worked for 16 months at Right Track CAD, a start-up company that specialized in place-and-route algorithms as well as FPGA architecture, at which point the company was acquired by Altera. He has worked with Altera since then, participating in both CAD algorithm and architecture development. Ketan is currently a supervisor responsible for development of portions of Altera's place-and-route technology.