Abstract
The arrival of System-on-a-Chip has introduced exciting research opportunities in system-level design, embedded system design and microchip physical design. Use of high-level languages such as SystemC is accelerating in both industry and universities. These languages enable the capture of design intent at a high level, including designs that employ intellectual property components from third parties. Following high-level capture, architectural options can be explored to assess the potential usefulness, performance and feasibility of the design intent. An example is an algorithm performing real-time signal processing in a video communications application. Implementation options and their relative merits can then be assessed (FPGA, embedded software, commercial-off-the-shelf chips and custom hardware). This session will start with a brief introduction to the world-recognized research support services of CMC. This will be followed by a description of the system-level design and verification tools and methodologies available to Canadian university researchers. Research opportunities will be identified. Questions and a discussion will be encouraged.
Biography
Peter A. Stokes is Senior Manager, Engineering Operations at CMC and hasover 18 years of experience supporting Canadian university microelectronics related research. Prior to CMC, Peter worked on cellular telephone technology at Novatel and in the area of satellite imaging at Dipix Systems. Peter is an Electronics Engineering Technologist and member of the IEEE.