Computer Engineering Cider Seminars

Contemporary FPGA synthesis is a multi-phase process which involves technology independent logic optimization followed by FPGA-specific mapping to a target FPGA technology. Conventional technology-independent transformations are often unable to optimize circuits with constraints and goals specific to FPGA architectures. This talk describes an FPGA-specific logic synthesis approach, which unites multi-level logic transformation, decomposition, and optimization techniques into a single synthesis framework. Our techniques are built upon a BDD-based logic decomposition system. With this system, both AND-OR decompositions and AND-XOR decompositions can be identified, resulting in large area savings for synthesized XOR-intensive circuits. To induce good decompositions, a maximum fanout free cone (MFFC) based partial clustering and collapsing technique is used. This step is followed by an area-minimizing variable partitioning heuristic which decomposes collapsed nodes into LUT-feasible sub-functions. We compare the quality of results obtained using our techniques with those of academic (BoolMap, SIS) and industry (Altera Quartus) FPGA synthesis tools. Experimental results indicate that the circuits generated by our techniques are not only smaller, but are also significantly faster than those synthesized by conventional FPGA synthesis tools. Furthermore, the computation times required by our techniques are significantly smaller than those of previous techniques.

Russell Tessier is an associate professor of electrical and computer engineering at the University of Massachusetts, Amherst. He received S.M. and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology. Dr. Tessier was a founder of Virtual Machine Works, a logic emulation company currently owned by Mentor Graphics. Prof. Tessier leads the Reconfigurable Computing Group at UMass. His research interests include computer architecture, field-programmable gate arrays, and system verification.