Abstract
This talk will examine the notion of adaptation and the impact that it has on both FPGA architecture and CAD. The distinguishing feature of an adaptive FPGA is its ability to change a logic block's functionality in response to changing circuit requirements. This ability is obtained at the expense of a small increase in FPGA area. However, this area increase is offset by significant reductions in the number of logic blocks required to implement a circuit. To exploit the unique features offered by the architecture, virtually every step of the CAD flow is modified. The talk will describe a set of CAD tools that perform synthesis, tech mapping, packing and placement for adaptive FPGAs.
Biography
Valavan Manohararajah is a PhD student in the computer group supervised by Prof. Z. G. Vranesic and Prof. S. Brown. His research is in the area of architecture and CAD for FPGAs.