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Logic optimization is the step of the VLSI design cycle where the designer performs modifications on a design (netlist) to satisfy different constraints such as area, power or delay. Recently, ATPG-based design rewiring techniques for logic optimization have gained increasing popularity when compared to symbolic ones. Most existing ATPG-based techniques attempt to optimize a design through a sequence of simple design rewiring operations. During each iteration of this procedure, some simple redundant logic is added in the design so that the target logic becomes redundant itself and it can be removed. In this talk we will present a novel ATPG-based design rewiring methodology that borrows from design error diagnosis and correction techniques and works in the opposite direction to what existing ATPG-based design rewiring procedures do. However, when design rewiring is viewed in this new direction it can be shown that it offers additional optimization gains. We apply our technique to delay and power optimization and we present examples and experiments that indicate the added potential of our approach. Andreas Veneris is an Assistant Professor of Electrical and Computer Engineering at the University of Toronto. He also holds an appointment with the Department of Computer Science . His research interests include the development of CAD tools for synthesis, optimization and testing of digital VLSI circuits and systems. In addition, he has an interest in algorithms and theoretical computer science. |