Abstract
Testing Data Retention Faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time- consuming due to the required pause time that needs to be intro- duced in the test session. In this talk, I will present three DFx solutions on accelerating those DRFs test. The first simplified the general Pause Test widely used in the current industry. The second developed a "retention-aware" test power model to speed up those DRFs during power-constrained test scheduling of multiple embedded SRAMs. The last DFx solution proposed a novel technique, referred to as Pre-Discharge Write Test Mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. All those DFx solutions will be supported and evaluated by various experimental results.
Biography
Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P.R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada.
During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada.
He holds one pending U.S. patent and publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements.