Abstract
As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" rectangular layouts, or through the use of generators that can generate these hard cores (such as Giles). In this talk, I will focus on an alternative approach: vendors supply a synthesizable RTL version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers in terms of speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or SoC. When the required amount of programmable logic is small, this ease of use may be more important than the increased overhead.
In this talk I will present several alternative architectures for our synthesizable cores, discuss some of the CAD implications of these architectures, and will present a proof-of-concept chip that we built that contains one of these cores.
Biography
Steve Wilton received the M.A.Sc. and Ph.D. degrees from the EECG group at the University of Toronto in 1992 and 1997 respectively, working with Zvonko Vranesic and Jonathan Rose. In 1997, he joined the Department of Electrical and Computer Engineering at the University of British Columbia, where he is now an Associate Professor. During 2003 and 2004, he was a Visiting Professor in the Department of Computing at Imperial College, London, U.K., and at the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium. His research focuses on the architecture of FPGAs and programmable logic cores, and the CAD tools that target these devices.