Computer Engineering Cider Seminars

Declarative Coordination and Concurrency Management with S-Net
Clemens Grelck
University of Amsterdam

Multi-sensor Integration: From Devices to Applications and Back
Zeljko Zilic
McGill University

Tsunami Simulation on FPGA and its Analysis Based on Statistical Model Checking
Masahiro Fujita
University of Tokyo

AMOLED TV Design: Beyond Conventional Circuit and System Design
Dr. G. Reza Chaji
CTO Ignis Innovation Inc.

HPCA 2012 Practice Talks
Sheng Ma
Cedomir Segulja
University of Toronto

A Framework for Reasoning about Inherent Parallelism in Modern Object-Oriented Languages
Andrew Craik
Oracle Labs, Brisbane, Australia
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GPU Architecture Challenges for Throughput Computing
Tor Aamodt
University of British Columbia (UBC)

Smarter Biochips
Duncan Elliott
University of Alberta

ARM processors
Bob Boys
ARM

Microprocessor verification/debugging in abstracted level and their application to post-silicon debugging
Masahiro Fujita
University of Tokyo

Living in interesting times: Disruptive trends in computer architecture
Bob Blainey
IBM, Toronto

An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
Alexander Finder
University of Bremen, Germany

Event-driven Consumer Programming
Sinisa Srbljic, Dejan Skvorc and Goran Delac
University of Zagreb, Croatia

Generating an Efficient Instruction Set Simulator from a Complete Property Suite
Ulrich Kuhne
University of Bremen, Germany

GPU-based Acceleration of a Monte Carlo Simulation for Photodynamic Therapy Treatment Planning: CUDA vs. hiCUDA
Wiliam Lo and David Han
University of Toronto, Canada

A Spatial Computing Architecture for Computational Circuits
David Grant
University of British Columbia, Canada

Hardware-Accelerated Formal Verification
Professor Masahiro Fujita
University of Tokyo, Japan

Parallel Computing from Specialty to Ubiquity
Khaled Z. Ibrahim
IRISA/INRIA, France

A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
Mike Butts
Ambric, Inc., Beaverton, Oregon, USA
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The next generation of SAT solvers
Robert Wille
University of Bremen, Germany

A hardware-software co-design approach
with separated verification/synthesis between computation and communication
Prof. Masahiro Fujita
University of Tokyo
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Test Pattern Generation for Large Industrial Circuits
Dr. Goerschwin Fey

Heterogeneous Multi-Processor Pipelines: A Novel System-on-Chip Method
Sri Parameswaran
University of New South Wales

Write off-loading: practical power management for data center storage
Dushyanth Narayanan
Microsoft Research, Cambridge, UK

From SAT to QBF
Marco Benedetti
Laboratoire d'Informatique Fondamentale d'Orlians, France

A Quadrature Bandpass Delta-Sigma ADC for a Multi-standard TV tuner
Richard Schreier
Analog Devices, Inc.
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Analog Circuit Design in Nanoscale CMOS Technologies -
Opportunities and Challenges
Trond Ytterdal
Norwegian University of Science and Technology
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Amalgam: a Reconfigurable Processor for Future Fabrication Processes
Nicholas Carter
University of Illinois at Urbana-Champaign
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ADL-driven Compiler-in-the-Loop Exploration of Processor Architectures
Nikil Dutt
University of California, Irvine

Electromagnetic Attacks on Wireless Devices and Implications for Security
Catherine Gebotys
University of Waterloo

Reducing Binary Decision Diagrams (BDDs) using SAT-solvers
Robert Wille
University of Bremen, Germany
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Power-aware RAM Mapping for FPGA Embedded Memory Blocks
Russell Tessier
University of Massachusetts, Amherst
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Accelerate Retention Tests for Embedded SRAMs
Baosheng Wang
ATI Technologies Inc.
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Design Considerations for Continuous-Time ADCs
Richard Schreir
Analog Devices Inc.
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Reconfigurable Computing : A Natural Solution
Erik Dirkx
VUB - Free University of Brussels

A case for 16-bit floating point numbers: image and media processing on FGPAs
Daniel Etiemble
University of Paris Sud
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Defect Tolerance for Yield Enhancement of FPGA Interconnect Using Fine-Grain and Coarse-Grain Redundancy
Anthony Yu
University of British Columbia

Distributed Radar Networks for Hazardous Weather Detection, Prediction, and Response
David J. McLaughlin
University of Massachusetts -Amherst

Abstraction, Reality Checks and RCU
Dr. Paul E. McKenney
IBM

Anonymity in P2P systems
Nikita Borisov
University of Illinois, Urbana-Champaign

Sting: an Automatic Defense System against Zero-day Worm Attacks
Dawn Song
Carnegie Mellon University

High-performance Cache Models
Alexandra Fedorova
Harvard University

Synthesizable Embedded Programmable Logic Cores
Steve Wilton
University of British Columbia

FPGA Logic Synthesis and Technology Mapping Using Binary Decision Diagrams
Russell Tessier
University of Massachussetts Amherst

Synthesis: Traditional and Beyond
David Mendel
Altera

An Overview of Advanced Timing Analysis Concepts
David Karchmer
Altera

Power-Aware Branch Prediction
Amirali Baniasadi
University of Victoria

Optimizations for the NIOS processor for the APEX architecture
Paul Metzgen
Altera European R&D Center

Cisco Routers for Residential Broadband Aggregation
Guy Fedorkow
Cisco

Stratix II Seminar
Ketan Padalia
Altera

Hardware Support for Prescient Instruction Prefetch
Tor Aamodt
University of Toronto

Magnetic Hard Disk Storage: Past, Present and Future
Dr. Lubomyr T. Romankiw
IBM T.J. Watson Research Center

Adaptive FPGA Architectures
Valavan Manohararajah
University of Toronto

Tools and Applications for Simulation and Rapid Prototyping in Research on Computer Architecture
Dr. Naraig Manjikian
Queen's University

Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs
Andy Ye
University of Toronto

Formal Verification of Hardware
Rolf Drechsler
University of Bremen

System-on-Chip Research Opportunities
Peter Stokes
Canadian Microelectronics Corporation

Computer Architecture Research in the CMU Impetus Group
Babak Falsafi
Carnegie Melon University

A Framework for Modeling and Optimization of Prescient Instruction Prefetch
Tor Aamodt
University of Toronto

Taking Silicon to the Next Level: Implementing 3D ICs and multilevel DRAM memories
Duncan Elliot
University of Alberta

Object Oriented Programming for Multiprocessor Performance
Jonathan Appavoo
University of Toronto

Nearest Neighbour Interconnect Architectures for Deep Submicrom FPGAs
Ajay Roopchansignh
University of Toronto

Design and Performance Analysis of a High Speed AWGN Communication Channel Emulator
Emmanuel Boutillon
University of South Brittany

Multi-Dispatch in the Java Virtual Machine: Design and Implementation
Paul Lu
University of Alberta

Using Sparse Crossbars within LUT Clusters
Guy Lemieux
University of Toronto

Design Optimization Based on Diagnosis Techniques
Andreas Veneris
University of Toronto

OpenMP fine grain parallelization of MPI programs: the NAS benchmarks on clusters of multiprocessors
Daniel Etiemble
University of Toronto

Cider Organizational Issues and a Short Technical Presentation: Rethinking Server Architecture Under Power Dissipation Constraints
Andreas Moshovos
University of Toronto