Documentation on the NUMAchine Multiprocessor

We have written a technical report that describes the NUMAchine architecture, outlines important aspects of its cache coherence protocol, and provides simulation results for parallel execution of a number of benchmark programs.

• Hierarchical HTML version of NUMAchine Technical Report
  
  
• Monolithic HTML version of NUMAchine Technical Report (103 Kbytes)
  
  
• PostScript version of NUMAchine Technical Report (451 Kbytes)
  
  
• PDF version of NUMAchine Technical Report (175 Kbytes)
  Note: some figures do not come out properly in the PDF.
  Grab the PostScript version instead for now.

• R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic and Z. Zilic , "The NUMAchine Multiprocessor", Proceedings of the 2000 International Conference on Parallel Processing, Toronto, August 2000.
  full paper, (PDF, 109k)

• A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic, "Design and Implementation of the NUMAchine Multiprocessor," Proceedings of the 35th IEEE Design Automation Conference, San Francisco, June 1998.
  full paper (PostScript, 160 Kbytes)
  full paper (PDF, 41 Kbytes)


• S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic, and S. Srbljic, "Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools," Proceedings of the 33rd IEEE Design Automation Conference, Las Vegas, June 1996.
  abstract
  full paper (PostScript, 177 Kbytes)
  full paper (PDF, 63 Kbytes)


• Z. Zilic, G. Lemieux, K. Loveless, S. Brown, and Z. Vranesic, "Designing for High Speed-Performance in CPLDs and FPGAs," Proc. 3rd Canadian Workshop on Field-Programable Devices (FPD'95): Technology, Tools, and Applications, Montreal, Canada, pp. 108 - 113, May 1995.
  full paper (PDF, 31 Kbytes)


• T. Abdelrahman, S. Brown, T. Mowry, K. Sevcik, M. Stumm, Z. Vranesic, S. Zhou, A. Elkateeb, M. Gusat, P. Pereira, B. Gamsa, R. Grindley, O Kreiger, G. Lemieux, K. Loveless, N. Manjikian, G. Ravindran, S. Srbljic, Z. Zilic "An Overview of the NUMAchine Multiprocessor Project," Proceedings of the 8th Canadian Supercomputing Conference, June 1994.
  full paper (PostScript, 224 Kbytes)
  full paper (PDF, 200 Kbytes)

We are developing the system-level programming documentation to provide details on the NUMAchine address space and describe various special functions controlled by system software.

• NUMAchine Principles of Operations for System Programmers (PDF, 228 Kbytes)
  DISCLAIMER: this is a preliminary document and is subject to change at anytime.

Also, the hardware reference manual describes all of those nitty-gritty details that the software types don't really care about. Those who work closely with the hardware should be familiar with this manual.

• NUMAchine Hardware Reference and Maintenance Manual (PDF, 539 Kbytes)
  DISCLAIMER: this is a preliminary document and is subject to change at anytime.

The following theses offer greater insight into the details of the NUMAchine hardware. However, note that the content of the theses is dated, and changes to the hardware have been made for various reasons (integration, economics, correctness, etc.). Consequently, the information below does not accurately document the state of the NUMAchine hardware as it is today. Instead, consult either the System Programming Manual or Hardware Reference and Maintenance Manual, as these will be kept as current as possible.


• Eddy Ah Pin, "Hardware Performance Monitoring in Memory of NUMAchine Multiprocessor," Undergraduate Thesis, University of Toronto, 1997.
  PDF, 146k


• Alex Grbic, "Hierarchical Directory Controllers in the NUMAchine Multiprocessor," M.A.Sc. Thesis, University of Toronto, 1996.
  PDF, 4120k


• Alex Grbic, "Assessment of Cache Coherence Protocols in Shared-Memory Multiprocessors," Ph.D. Thesis, University of Toronto, 2003.
  PDF, 1064k


• Robin Grindley, "The NUMAchine Multiprocessor: Design and Analysis," Ph.D. Thesis, University of Toronto, 1999.
  PDF, 1776k


• Guy Lemieux, "Hardware Performance Monitoring in Multiprocessors," M.A.Sc. Thesis, University of Toronto, 1996.
  PDF, 219k


• Kelvin Loveless, "The Implementation of Flexible Interconnect in the NUMAchine Multiprocessor," M.A.Sc. Thesis, University of Toronto, 1996.
  PDF, 848k


• Karl Schabas, "The Implementation of Basic Monitoring Functions on the NUMAchine Multiprocessor", Undergraduate Thesis, University of Toronto, 2000.
  PDF, 281K

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