iFAR intelligent FPGA Architecture Repository

The intelligent FPGA Architecture Repository (iFAR) website contains accurate area and timing estimates for the logic and routing of varied island-style FPGA architectures. Within this repository one can find areas and delays for architectures with varied logic block parameters, such as LUT size, and routing parameters such as segment length. The area and delay is determined through careful transistor sizing of each architecture. This is done for both a range of past, current and future implementation technologies (ranging from 22 nm to 180 nm CMOS) and a range of design objectives with varying emphasis on performance or area/cost.

The creation of architecture files for a range of different optimization objectives adds a significant new axis to explore. Conventionally, only a single objective, such as minimizing the area delay product of a circuit design, has been considered but it is also advantageous to use transistor-level designs that have been optimized with a great emphasis on area or delay. For each architecture in the repository, the objective function that was minimized is listed as areabdelayc. A greater value of k or n means a greater emphasis on area or performance respectively. More details about the optimization and the range of architectures possible can be found in reference [1].

The area and delay estimates are provided in a form that enables them to be easily used with the standard FPGA architecture experimentation tool, VPR. When using these area and delay models please reference [1] and this website.

Proceed to the iFAR Listing

References

[1] Ian Kuon and Jonathan Rose, "Area and Delay Trade-offs in the Circuit and Architecture Design of FPGAs", International Symposium on FPGAs, 2008, pp 149--158 DOI

[2] Ian Kuon and Jonathan Rose, "Automated Transistor Sizing for FPGA Architecture Exploration", Design Automation Conference (DAC), Anaheim, CA, 2008, pp 792--795, DOI.

News

2008/02/20 Release of the first architectures into the repository

Acknowledgements

Funding for this project has been generously provided by NSERC

The transistor-level models used to determine these area and delays were obtained from/through: