ANDREW CANIS andrewcanis.com
andrewcanis@gmail.com

EDUCATION
Ph.D. Computer Engineering
University of Toronto, Toronto, Ontario Jan. 2011 - 2015
  • Thesis: LegUp: Open-Source High-Level Synthesis Research Framework
  • Advisors: Jason Anderson and Stephen Brown

M.A.Sc Computer Engineering
University of Toronto, Toronto, Ontario Sept. 2008 - Dec. 2010
  • Transferred to the Ph.D. program in Jan. 2011

B.Sc Computer Engineering (Honours with Distinction)
University of Waterloo, Waterloo, Ontario Sept. 2003 - June 2008
  • Dean's Honour List: 4 of 7 academic terms

PUBLICATIONS
Refereed Journal Publications (Published, Accepted or Minor Revisions)
  1. Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J.H. Anderson, "The effect of compiler optimizations on high-level synthesis-generated hardware," ACM Transactions on Reconfigurable Technology and Systems (TRETS), September, 2013. (19 page manuscript in minor revisions).
  2. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, T. Czajkowski, S. D. Brown, and J. H. Anderson, "LegUp: An Open Source High-Level Synthesis Tool for FPGA-Based Processor/Accelerator Systems," ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 2, p. 24, 2013. (25 page manuscript).
Refereed International Conference Publications (Accepted or Published)
  1. A. Canis, J.H. Anderson, S.D. Brown, "Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis," Int'l Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September, 2014. (In press).
  2. B. Fort, A. Canis, J. Choi, N. Calagar, R. Lian, S. Hadjis, Y.T. Chen, M. Hall, B. Syrowik, T. Czajkowski, S.D. Brown, J.H. Anderson "Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis," Int'l Conference on Embedded and Ubiquitous Computing (EUC), Milan, Italy, August 2014. (Invited paper).
  3. A. Canis, J. Choi, B. Fort, R. Lian, Q. Huang, N. Calagar, M. Gort, J.J. Qin, M. Aldham, T. Czajkowski, S.D. Brown, J.H. Anderson, "From Software to Accelerators with LegUp High-Level Synthesis," Int'l Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Montreal, September 2013. (Invited Paper).
  4. Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J. Anderson, "The effect of compiler optimizations on high-level synthesis for FPGAs," IEEE Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, WA, May 2013.
  5. A. Canis, S. D. Brown, and J. H. Anderson, "Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis," Design, Automation, and Test in Europe (DATE), Grenoble, France, March, 2013.
  6. J. Choi, K. Nam, A. Canis, J.H. Anderson, S.D. Brown, and T. Czajkowski, "Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems," IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, Canada, April 2012.
  7. S. Hadjis, A. Canis, J. Anderson , J. Choi , K. Nam, S. Brown, T. Czajkowski, "Impact of FPGA Architecture on Resource Sharing in High-Level Synthesis," ACM/SIGDA Int'l Symp. on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2012.
  8. M. Aldham, J.H. Anderson, S. Brown, A. Canis. "Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Embedded Processors. IEEE Int'l Conf. on Application-specific Systems, Architectures and Processors (ASAP), Santa Monica, CA, Sept. 2011.
  9. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. Anderson, S. Brown, and T. Czajkowskiz. LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems. In Proc. ACM/SIGDA Intern. Symp. on Field-Programmable Gate Arrays (FPGA), 2011. (Citations: 123)
Magazine Articles (Unrefereed), Design Competitions:
  1. J. C. Cai, R. Lian, M. Wang, A. Canis, J. Choi, B. Fort, E. Hart, E. Miao, Y. Zhang, N. Calagar, S. D. Brown, J. H. Anderson, "From C to Blokus Duo with LegUp High-Level Synthesis," Int'l Conf. on Field-Programmable Technology (FPT), Kyoto, Japan 2013.
  2. "Discoveries are Made with Teamwork: From Software to Circuits with LegUp," ANNUM, University of Toronto, December 2013.

SOFTWARE ARTIFACTS RELEASED
LegUp: Open-Source High-Level Synthesis Tool
University of Toronto, Toronto, Ontario Mar. 2011 - Present
  • Downloaded by over 1000 research groups from outside the University of Toronto
  • The only robust open-source high-level synthesis tool for academics
  • Software freely available at: www.LegUp.org

INVITED TALKS & LECTURES
Conference Talks
  1. A. Canis, J.H. Anderson, S.D. Brown, "Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis," Int'l Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September, 2014 (To appear).
  2. A. Canis, Stephen D. Brown, and Jason H. Anderson, "Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis," Design, Automation, and Test in Europe (DATE). Grenoble, France, March, 2013.
  3. J.H. Anderson, S.D. Brown, A. Canis, J. Choi, "High-level synthesis with LegUp: a crash course for users and researchers", a 2.5 hour tutorial delivered at the ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 2013.
  4. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. Anderson, S. Brown, and T. Czajkowskiz. "LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems," ACM Int'l Symp. on Field-Programmable Gate Arrays (FPGA), 2011.
Invited Talks
  1. A. Canis, J. Choi, J.H. Anderson, "LegUp: An Open Source High-Level Synthesis Tool for FPGA-Based Processor/Accelerator Systems," Xilinx Inc., San Jose, February, 2013.
  2. J.H. Anderson, A. Canis, "LegUp FPGA high-level synthesis: overview and approaches for resource reduction," Intel Research Labs, Hillboro, Oregon, August 2012.
  3. A. Canis, "LegUp: A Self-Accelerating Adaptive Processor", Cascadia 2010: A joint workshop of UBC, SFU, and UWash on FPGA Research, UBC, Aug. 12, 2010.
  4. A. Canis and J. Anderson, "A Self-Accelerating Adaptive Processor", Regional Workshop on Better Prog. Models for FPGAs, University of Toronto, May 17, 2010
  5. A. Canis and M. Aldham, "High-Level Synthesis Evaluation: xPilot and ImpulseC", Monthly FPGA Seminar, University of Toronto, January 21, 2010.

AWARDS & HONOURS
Title Amount Year
NSERC CGS Postgraduate Scholarship - PhD $70,000 2012 - 2014
Ontario Graduate Scholarship $15,000 2011 - 2012
Edward Rogers Sr. Grad Scholarship $5,000 2009 - 2010
NSERC Canada Graduate Scholarship - Masters $35,000 2008 - 2010
Savvas Chamberlain Scholarship $3,000 2007
Faculty of Engineering Entrance Scholarship 2003 - 2004
Governor General's Gold (Secondary School) Medal 2003

WORK EXPERIENCE
Co-Founder & CEO
LegUp Computing, Toronto, ON May 2015 - Present
  • Commercializing Ph.D. research on LegUp high-level synthesis
  • Working closely with FPGA vendors to produce a C-based design flow
  • Company website: www.LegUpComputing.com

Circuit Optimization Researcher
Sun Labs, Melo Park, CA Sept - Dec 2007, May - Aug 2009
  • Worked with researchers using convex optimization methods to resize standard cells
  • Produced graphs illustrating trade-off between delay and power for Sun circuit designers

Hardware Engineering
Altera Corporation, Toronto, ON May - Aug 2006, Jan - Apr 2007
  • Investigated circuit transformations aimed at increasing clock speed across large circuits
  • Implemented a multiplexer resynthesis algorithm that improved clock speed performance

Undergrad Research Assistant
University of Waterloo, Waterloo, ON May 2007 - May 2008
  • Advisor: Mark Aagaard
  • Developing an eclipse-based java toolkit for educational circuit exploration with VHDL
  • Wrote a false path timing analyser for simple combinational circuits with 2-input gates


TEACHING EXPERIENCE
Teaching Assistant
University of Toronto, Toronto, ON Jan. 2009 - 2015
  • Lab TA for ECE 241 (Fall) and ECE 342 (Winter) teaching hardware design
  • Gave weekly tutorials for APS 105 (Computer Fundamentals) - Fall, 2012
  • Lectures: APS 105 (2 classes in Oct, 2012), ECE 241 (3 classes in Oct, 2011)

Tutorial Instructor
UW Asic Design Team, Waterloo, ON May 2005 - December 2006
  • Coordinated and taught digital logic and VHDL tutorials to first year engineering students

PROFESSIONAL ACTIVITIES
  • Primary reviewer for the Journal of Electrical and Computer Engineering 2011
  • Secondary reviewer for: ICCAD'14, FCCM'14, ICCAD'13, FCCM'13, FPT'11, FPL'11, FCCM'11, ISCAS'11, FPGA'10, FPL'09, WoSPS'08
  • Mentored summer undergraduate research students working on the LegUp project (2011-14)
  • Organized FPGA Reading Group (FPGARG) weekly talks during Fall 2009