Disclaimer:The patent summary and comments in this page are only based on my understanding of the patent. I might be wrong! Please do not hessitate to send me an email to email@example.com if you have any comments.
Note: In this page, FE is used synonymously with Ferroelectric, cap with capacitance and capacitor, BL with bitline, WL with wordline, and PL and DL for plateline and driveline.
Feb. 97, NEC Corporation, 5 600 587
Ferroelectric Random Access Memory
Summary: This patent suggests using two blocks of ferro arrays, each with a separte set of platelines running parallel to bitlines. In the voltile mode, the platelines of one block are set at Vdd and the platelines of the other block are set at Vss! In the nonvolatile mode, the corresponding platelines of the two blocks are shorted together at Vdd/2 and a non-driven plateline scheme is implemented. For a reference on non-driven plateline scheme, click on Selected Bibliography at the end of this page.
Comments: Based on the explanation provided in the patent, the operation in the non-volatile mode is questionable. The patent suggests deactivating the wordline while the bitline and the plateline are both Vdd/2! If the platelines remain at Vdd/2 for the next access, then one must refresh the memory to avoid the storage node falling from Vdd/2! Also, operating the memory in the volatile mode for a long time has imprint effects.
Voltage Raference for a Ferroelectric 1T/1C Based Memory
Summary: For reference generation, this patent suggests using two dummy cells each having a cell-sized FE cap (one precharged to 0, one precharged to 1) and connecting them to two adjacent coulumns (bitline pairs)! The ratio of dummy cell cap to bitline cap is the same as memory cell cap to bitline cap. By asserting the ref wordline, a voltage reference is generated on the corresponding bitlines for the two columns at the same time. Note that this votage is half way between the voltage generated by a cell storing a 0 and that of a cell storing a 1.
Comments: The FE caps of dummy cells are accessed more frequently compared to FE caps of regular cells. Hence, they fatigue faster! Unless you are using a fatigue-free FE material.
Semiconductor Memory Device Having FE Capacitor Memory Cells with Reading, Writing, and Forced Refreshing Functions and a Method of Operating the same
Ferroelectric Memory Sensing Scheme Using Bit Lines Precharged to a Logic One Voltage
Summary: Step-sensing scheme is faster than the pulse-sensing scheme because it only requires one transition of the plate-line before sensing is possible. But pulse-sensing scheme is more robust to a downward/upward shift of the hysteresis loop. This patent provides a method that compromises between the two methods by precharging the bitline to Vdd instead of Vss.
Folded Bit Line Ferroelectric Memory Device
Summary: This patent suggests using two half-sized FE capacitors initilized at 0 and 1 to dump thier charge on a bitline, hence generating a reference voltage for the other bitline.
Comments: It seems Ramtron (Nov. 96: 5 572 459) offers a similar, but better solution for the reference voltage generation.
Summary: A ferrolectric memory is used in a volatile mode similar to DRAM until the power shuts off. At this time, it will store its information in a nonvolatile mode. Very similar to shadow SRAM idea!
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This page is maintained by Ali Sheikholeslami. Created on July 4, 1997. Last modified on July 19, 2000.