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Spin Electronics: STT-MRAM


A Verilog-A Model Available for Download

Here is a Verilog-A model for Magnetic Tunnel Junctions. This model is referenced in [J23] below.

Click here Verilog-A-Codes.txt to download.


Our Latest Publications on Spintronics:

[J23] A. Vatankhahghadim, S. Huda, and A. Sheikholeslami,
A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 61, No. ?, pp. 1-10, to appear in 2014.

[J20] S. Huda* and A. Sheikholeslami,
A Novel STT-MRAM Cell With Disturbance-Free Read Operation
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 60, No. 6, pp. 1534-1547, June 2013.

[C25] D. Halupka*, S. Huda*, W. Song*, A. Sheikholeslami, K. Tsunoda, C. Yoshida, and M. Aoki,
Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13um CMOS,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 256-257, Feb. 2010.


For a complete list of publications, please refer to Publications and Patents.

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