Current Research Activities

My research focus is in the area of CAD for EDA. I specifically focus on FPGAs, though most of my work can also be seemlessly applied to ASICs. Currently, I am focusing on scalable synthesis and RTL-synthesis methods. I have been working on FBDD and trying to improve it in terms of running time and synthesis quality.

I currently am very active in research discussions and am part of the FPGA reading group and attend most cider seminars and distinguished lectures held at the University of Toronto.

Previous Research Activities

I received my Master's of Applied Science from the University of Toronto in September of 2005. Here, I applied Boolean Satisfiability (SAT) to FPGA logic synthesis. At the end of my Master's, I successfully created a SAT based technology mapper for FPGAs, a programmable logic block evaluation tool, and an optimality study on current state-of-the-art technology mappers.

I have also worked at the Altera Toronto Technology Centre in physical design where I upgraded a commercial physical synthesis tool to support structured-ASICs. Here, I was responsible for upgrading the incremental placer to support standard cells.

I have also done security research at a biometric start up company called SAFLINK. During my time there, I was chosen to assess the security quality of various biometric secured operating systems with the assumption that I have physical access to all computer terminals. During my analysis, I was able to fool the system that I was the network administrator and broke into the network in under two days.

Last updated Apr 2006