.model cp0IntEncoder_comb_opt_2in
.inputs Phi10 Reset_s10 Reset_s20 Stall_s10 Interrupt_w<0>0 Interrupt_w<1>0 \
 Interrupt_w<2>0 Interrupt_w<3>0 Interrupt_w<4>0 Interrupt_w<5>0 \
 Except_s1w0 AIsBoosted_s1m0 BIsBoosted_s1m0 InstrIsLoad_s1m0 \
 InstrIsStore_s1m0 AALUOvfl_s1m0 BALUOvfl_s1m0 BIsBoosted_s2m0 \
 InstrIsLoad_s2m0 AIsBoosted_s2m0 AALUOvfl_s2m0 Int_s2<0>0 Int_s2<1>0 \
 Int_s2<2>0 Int_s2<3>0 Int_s2<4>0 Int_s2<5>0 BALUOvfl_s2m0 \
 InstrIsStore_s2m0 AIsBoosted_s2e0 BIsBoosted_s2e0 AALUOvfl_v2e0 \
 BALUOvfl_v2e0 ExceptionCause_v2<0>0 ExceptionCause_v2<1>0 \
 ExceptionCause_v2<2>0 ExceptionCause_v2<3>0 ExceptionCause_v2<4>0 \
 ExceptionCauseTmp_s1w<0>0 ExceptionCauseTmp_s1w<1>0 \
 ExceptionCauseTmp_s1w<2>0 ExceptionCauseTmp_s1w<3>0 \
 ExceptionCauseTmp_s1w<4>0 Int_s1<0>0 Int_s1<1>0 Int_s1<2>0 Int_s1<3>0 \
 Int_s1<4>0 Int_s1<5>0 TLBL1_s1w0 SetBoost_s1w0 BExTaken_s1w0 \
 TLBRefill_v2m0 TLBInvalid_v2m0 MemExcept_s2m0 IntPending_s2<0>0 \
 IntPending_s2<1>0 IntMask_s2<0>0 IntMask_s2<1>0 IntMask_s2<2>0 \
 IntMask_s2<3>0 IntMask_s2<4>0 IntMask_s2<5>0 IntMask_s2<6>0 IntMask_s2<7>0 \
 IEc_s20 Syscall_s2m0 Break_s2m0 TLBModified_v2m0
.outputs _n1690 _n16b0 _n16d<0>0 _n16d<1>0 _n16d<2>0 _n16d<3>0 _n16d<4>0 \
 _n16f<0>0 _n16f<1>0 _n16f<2>0 _n16f<3>0 _n16f<4>0 ExceptionCause_s1w<0>0 \
 ExceptionCause_s1w<1>0 ExceptionCause_s1w<2>0 ExceptionCause_s1w<3>0 \
 ExceptionCause_s1w<4>0 SeqExcept_v20 _n1710 _n1730 _n175<0>0 _n175<1>0 \
 _n175<2>0 _n175<3>0 _n175<4>0 _n175<5>0 _n1770 _n1790 _n17b<0>0 _n17b<1>0 \
 _n17b<2>0 _n17b<3>0 _n17b<4>0 _n17b<5>0 _n17d0 _n17f0 BoostedExcept_v20 \
 _n1810 _n1830 _n1850 _n1870 _n1890 ExceptionCauseTmp_s1w$raw_n0<0>0 \
 Int_s2$raw_nd<1>0 BIsBoosted_s2m$raw_nb0 ExceptionCauseTmp_s1w$raw_n0<3>0 \
 ExceptionCause_v2$raw_n1<0>0 Int_s2$raw_nd<4>0 Int_s1$raw_ne<4>0 \
 ExceptionCause_v2$raw_n1<3>0 InstrIsLoad_s2m$raw_n20 Int_s1$raw_ne<1>0 \
 BALUOvfl_s1m$raw_n60 AIsBoosted_s2m$raw_n90 \
 ExceptionCauseTmp_s1w$raw_n0<1>0 AALUOvfl_s2m$raw_n50 Int_s2$raw_nd<2>0 \
 ExceptionCauseTmp_s1w$raw_n0<4>0 ExceptionCause_v2$raw_n1<1>0 \
 Int_s2$raw_nd<5>0 Int_s1$raw_ne<3>0 BIsBoosted_s1m$raw_na0 \
 ExceptionCause_v2$raw_n1<4>0 Int_s1$raw_ne<0>0 Int_s2$raw_nd<0>0 \
 Reset_s2$raw_nf0 BALUOvfl_s2m$raw_n70 ExceptionCauseTmp_s1w$raw_n0<2>0 \
 Int_s2$raw_nd<3>0 Int_s1$raw_ne<5>0 TLBL1_s1w$raw_n100 \
 InstrIsStore_s2m$raw_n30 AALUOvfl_s1m$raw_n40 ExceptionCause_v2$raw_n1<2>0 \
 Int_s1$raw_ne<2>0 SetBoost_s1w$raw_nc0 AIsBoosted_s1m$raw_n80
.names BIsBoosted_s2m0 Break_s2m0 Reset_s20 TLBModified_v2m0 _106
110- 1
1-01 1
.names AALUOvfl_s2m0 AIsBoosted_s2m0 Reset_s20 _109
110 1
.names _80 _87 _n16d<3>0 _156
110 1
.names Reset_s20 _82 _87 _n16d<3>0 _159
0100 1
.names _80 _ndf0 _ne40 _n16d<3>0 _164
1010 1
.names BIsBoosted_s2m0 _474 _516 _523 _171
1100 1
.names BALUOvfl_s2m0 BIsBoosted_s2m0 Reset_s20 Syscall_s2m0 _221
-101 1
110- 1
.names BIsBoosted_s2m0 InstrIsLoad_s2m0 InstrIsStore_s2m0 MemExcept_s2m0 \
 Reset_s20 TLBInvalid_v2m0 TLBRefill_v2m0 _226
1-1-0-1 1
11--0-1 1
1-1-01- 1
11--01- 1
1-110-- 1
11-10-- 1
.names _77 _nd00 _nd50 _n16d<3>0 _428
1-01 1
11-1 1
.names BIsBoosted_s2m0 Break_s2m0 _80 _92 _469
011- 1
--11 1
.names Reset_s20 _86 _n8f0 _nd50 _474
0000 1
.names Break_s2m0 TLBModified_v2m0 _87 _481
000 1
.names Break_s2m0 TLBModified_v2m0 _87 _92 _482
0000 1
.names _516 _523 _80 _82 _487
0010 1
.names IEc_s20 IntMask_s2<0>0 IntMask_s2<1>0 IntMask_s2<2>0 IntMask_s2<3>0 \
 IntPending_s2<0>0 IntPending_s2<1>0 Int_s2<0>0 Int_s2<1>0 _516
1---1---1 1
1--1---1- 1
1-1---1-- 1
11---1--- 1
.names IEc_s20 IntMask_s2<4>0 IntMask_s2<5>0 IntMask_s2<6>0 IntMask_s2<7>0 \
 Int_s2<2>0 Int_s2<3>0 Int_s2<4>0 Int_s2<5>0 _523
1---1---1 1
1--1---1- 1
1-1---1-- 1
11---1--- 1
.names AALUOvfl_s2m0 AIsBoosted_s2m0 _77
0- 1
-1 1
.names TLBInvalid_v2m0 TLBRefill_v2m0 _78
-1 1
1- 1
.names Reset_s20 _n8f0 _80
00 1
.names BIsBoosted_s2m0 InstrIsLoad_s2m0 InstrIsStore_s2m0 _78 _82
01-1 1
0-11 1
.names AALUOvfl_s2m0 AIsBoosted_s2m0 BALUOvfl_s2m0 BIsBoosted_s2m0 _86
--10 1
10-- 1
.names BIsBoosted_s2m0 InstrIsLoad_s2m0 InstrIsStore_s2m0 MemExcept_s2m0 \
 _87
01-1 1
0-11 1
.names BALUOvfl_s2m0 BIsBoosted_s2m0 Syscall_s2m0 _77 _92
-01- 1
10-- 1
---0 1
.names Phi10 Stall_s10 _n1a0
10 1
.names InstrIsLoad_s2m0 InstrIsStore_s2m0 TLBInvalid_v2m0 TLBRefill_v2m0 \
 _n8f0
00-1 1
001- 1
.names BALUOvfl_s2m0 BIsBoosted_s2m0 _nd00
10 1
.names BIsBoosted_s2m0 Syscall_s2m0 _nd50
01 1
.names BIsBoosted_s2m0 InstrIsLoad_s2m0 MemExcept_s2m0 _ndf0
011 1
.names BIsBoosted_s2m0 InstrIsStore_s2m0 MemExcept_s2m0 _ne40
011 1
.names BIsBoosted_s2m0 InstrIsLoad_s2m0 TLBInvalid_v2m0 TLBRefill_v2m0 \
 _ne90
01-1 1
011- 1
.names BIsBoosted_s1m0 BIsBoosted_s2m0 Except_s1w0 _n1a0 _n1690
1-01 1
110- 1
-1-0 1
.names Except_s1w0 InstrIsLoad_s1m0 InstrIsLoad_s2m0 _n1a0 _n16b0
01-1 1
011- 1
--10 1
.names BIsBoosted_s2m0 InstrIsStore_s2m0 TLBModified_v2m0 _164 _428 _78 _80 \
 _ndf0 _ne90 _n16d<3>0 _n16d<0>0
01---11000 1
0-1---1000 1
----1----- 1
---1------ 1
.names Reset_s20 _159 _n8f0 _n16d<4>0 _n16d<1>0
0-1- 1
---1 1
-1-- 1
.names _156 _86 _n16d<3>0 _n16d<4>0 _n16d<2>0
-11- 1
---1 1
1--- 1
.names _171 _469 _482 _487 _n16d<3>0
--11 1
-1-- 1
1--- 1
.names _171 _481 _487 _92 _n16d<4>0
-110 1
1--- 1
.names ExceptionCauseTmp_s1w<0>0 ExceptionCause_v2<0>0 Phi10 _n16f<0>0
-10 1
1-1 1
11- 1
.names ExceptionCauseTmp_s1w<1>0 ExceptionCause_v2<1>0 Phi10 _n16f<1>0
-10 1
1-1 1
11- 1
.names ExceptionCauseTmp_s1w<2>0 ExceptionCause_v2<2>0 Phi10 _n16f<2>0
-10 1
1-1 1
11- 1
.names ExceptionCauseTmp_s1w<3>0 ExceptionCause_v2<3>0 Phi10 _n16f<3>0
-10 1
1-1 1
11- 1
.names ExceptionCauseTmp_s1w<4>0 ExceptionCause_v2<4>0 Phi10 _n16f<4>0
-10 1
1-1 1
11- 1
.names BExTaken_s1w0 ExceptionCauseTmp_s1w<0>0 ExceptionCause_s1w<0>0
01 1
.names BExTaken_s1w0 ExceptionCauseTmp_s1w<1>0 ExceptionCause_s1w<1>0
-1 1
1- 1
.names BExTaken_s1w0 ExceptionCauseTmp_s1w<2>0 ExceptionCause_s1w<2>0
-1 1
1- 1
.names BExTaken_s1w0 ExceptionCauseTmp_s1w<3>0 ExceptionCause_s1w<3>0
-1 1
1- 1
.names BExTaken_s1w0 ExceptionCauseTmp_s1w<4>0 ExceptionCause_s1w<4>0
01 1
.names _n16d<4>0 SeqExcept_v20
0 1
.names AIsBoosted_s1m0 AIsBoosted_s2m0 Except_s1w0 _n1a0 _n1710
1-01 1
110- 1
-1-0 1
.names BALUOvfl_s1m0 BALUOvfl_v2e0 Phi10 _n1730
-10 1
1-1 1
11- 1
.names Int_s2<0>0 Interrupt_w<0>0 Phi10 Stall_s10 _n175<0>0
-110 1
1-0- 1
11-- 1
1--1 1
.names Int_s2<1>0 Interrupt_w<1>0 Phi10 Stall_s10 _n175<1>0
-110 1
1-0- 1
11-- 1
1--1 1
.names Int_s2<2>0 Interrupt_w<2>0 Phi10 Stall_s10 _n175<2>0
-110 1
1-0- 1
11-- 1
1--1 1
.names Int_s2<3>0 Interrupt_w<3>0 Phi10 Stall_s10 _n175<3>0
-110 1
1-0- 1
11-- 1
1--1 1
.names Int_s2<4>0 Interrupt_w<4>0 Phi10 Stall_s10 _n175<4>0
-110 1
1-0- 1
11-- 1
1--1 1
.names Int_s2<5>0 Interrupt_w<5>0 Phi10 Stall_s10 _n175<5>0
-110 1
1-0- 1
11-- 1
1--1 1
.names AALUOvfl_s1m0 AALUOvfl_s2m0 Except_s1w0 _n1a0 _n1770
1-01 1
110- 1
-1-0 1
.names BIsBoosted_s1m0 BIsBoosted_s2e0 Phi10 _n1790
-10 1
1-1 1
11- 1
.names Int_s1<0>0 Int_s2<0>0 Phi10 _n17b<0>0
-10 1
1-1 1
11- 1
.names Int_s1<1>0 Int_s2<1>0 Phi10 _n17b<1>0
-10 1
1-1 1
11- 1
.names Int_s1<2>0 Int_s2<2>0 Phi10 _n17b<2>0
-10 1
1-1 1
11- 1
.names Int_s1<3>0 Int_s2<3>0 Phi10 _n17b<3>0
-10 1
1-1 1
11- 1
.names Int_s1<4>0 Int_s2<4>0 Phi10 _n17b<4>0
-10 1
1-1 1
11- 1
.names Int_s1<5>0 Int_s2<5>0 Phi10 _n17b<5>0
-10 1
1-1 1
11- 1
.names BALUOvfl_s1m0 BALUOvfl_s2m0 Except_s1w0 _n1a0 _n17d0
1-01 1
110- 1
-1-0 1
.names Phi10 Reset_s10 Reset_s20 _n17f0
0-1 1
11- 1
-11 1
.names _106 _109 _221 _226 BoostedExcept_v20
1--- 1
---1 1
-1-- 1
--1- 1
.names AALUOvfl_s1m0 AALUOvfl_v2e0 Phi10 _n1810
-10 1
1-1 1
11- 1
.names Except_s1w0 InstrIsStore_s1m0 InstrIsStore_s2m0 _n1a0 _n1830
01-1 1
011- 1
--10 1
.names Phi10 TLBL1_s1w0 _n8f0 _n1850
0-1 1
11- 1
-11 1
.names AIsBoosted_s2m0 BIsBoosted_s2m0 Phi10 SetBoost_s1w0 _n1870
-10- 1
1-0- 1
--11 1
-1-1 1
1--1 1
.names AIsBoosted_s1m0 AIsBoosted_s2e0 Phi10 _n1890
-10 1
1-1 1
11- 1
.names ExceptionCauseTmp_s1w$raw_n0<0>0
.names Int_s2$raw_nd<1>0
.names BIsBoosted_s2m$raw_nb0
.names ExceptionCauseTmp_s1w$raw_n0<3>0
.names ExceptionCause_v2$raw_n1<0>0
.names Int_s2$raw_nd<4>0
.names Int_s1$raw_ne<4>0
.names ExceptionCause_v2$raw_n1<3>0
.names InstrIsLoad_s2m$raw_n20
.names Int_s1$raw_ne<1>0
.names BALUOvfl_s1m$raw_n60
.names AIsBoosted_s2m$raw_n90
.names ExceptionCauseTmp_s1w$raw_n0<1>0
.names AALUOvfl_s2m$raw_n50
.names Int_s2$raw_nd<2>0
.names ExceptionCauseTmp_s1w$raw_n0<4>0
.names ExceptionCause_v2$raw_n1<1>0
.names Int_s2$raw_nd<5>0
.names Int_s1$raw_ne<3>0
.names BIsBoosted_s1m$raw_na0
.names ExceptionCause_v2$raw_n1<4>0
.names Int_s1$raw_ne<0>0
.names Int_s2$raw_nd<0>0
.names Reset_s2$raw_nf0
.names BALUOvfl_s2m$raw_n70
.names ExceptionCauseTmp_s1w$raw_n0<2>0
.names Int_s2$raw_nd<3>0
.names Int_s1$raw_ne<5>0
.names TLBL1_s1w$raw_n100
.names InstrIsStore_s2m$raw_n30
.names AALUOvfl_s1m$raw_n40
.names ExceptionCause_v2$raw_n1<2>0
.names Int_s1$raw_ne<2>0
.names SetBoost_s1w$raw_nc0
.names AIsBoosted_s1m$raw_n80
.end