Andrew C. Ling, Jianwen Zhu, and Stephen D. Brown, Scalable Technology Mapping and Clustering Techniques using Decision Diagrams.in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, Vol. 27, No. 3, March 2008, pp. 423-435 (IEEE Explore).
Andrew C. Ling, Deshanand P. Singh, and Stephen D. Brown, FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability. in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, Vol. 26, No. 7, July 2007, pp. 1196-1210 (IEEE Explore)
Andrew C. Ling, Deshanand P. Singh and Stephen D. Brown, FPGA PLB Evaluation using Quantified Boolean Satisfiability. in IEE Proceedings on Computers and Digital Techniques, Volume 153, Number 3, May 2006, pp. 165-172. ISSN 1350-2387 Invited Journal Paper, (pdf).
A.C. Ling, S.D. Brown, J. Zhu, and S. Safarpour. Towards Automated ECOs for FPGAs. In International Symposium on FPGA (FPGA'09), 2009.
A.C. Ling, J. Zhu, and S.D. Brown. Structural Metrics for Congestion Driven Logic Synthesis. In International Workshop on Logic and Synthesis (IWLS'08), 2008, (pdf).
A.C.Ling, J. Zhu, and S.D.Brown. Delay Drive AIG Restructuring using Slack Budget Management. in GLS-VLSI'08: Proceedings of the 2008 conference on Great Lake Symposium on VLIS, Orlando, Florida, USA, May 2008 (pdf)
A.C.Ling, D.P.Singh, and S.D.Brown. Incremental Placement for Structured ASICs using the Transportation Problem. in VLSI-SoC'07, Atlanta, Georgia, USA, Oct 2007, pp 172-177 (pdf).
A.C.Ling, J. Zhu, and S.D.Brown. BddCut: Towards Scalable Symbolic Cut Enumeration. in ASP-DAC'07: Proceedings of the 2007 conference on Asia South Pacific Design Automation, Yokohama, Japan, Jan 2007, pp 408-413, (pdf, ppt).
A.C.Ling, D.P.Singh, and S.D. Brown. FPGA Technology Mapping: A Study of Optimality. In Proceedings of the 42nd Design Automation Conference (DAC'05), 2005, pp 427-432. Nominated for best paper in '05, (pdf, ppt).
A.C. Ling, D.P. Singh, V. Manohararajah, and S.D. Brown. FPGA Architecture Evaluation and Technology Mapping using Boolean Satisability. In International Workshop on Logic and Synthesis (IWLS'05), 2005, (pdf, ppt).
A.C. Ling, D.P.Singh, and S.D. Brown. FPGA Logic Synthesis using Quantified Boolean Satisability. In SAT '05: The Seventh International Conference on Theory and Applications of Satisfiability Testing, June 2005, pp 444-450, (pdf, ppt, intro slides).
A.C. Ling and D.P.Singh. (2005) Incremental Placement for Hardcopy II using the Transportation Problem. Submitted Sept 2005 to the US patent office
A.C. Ling and D.P. Singh. (2005) FPGA architecture evaluation methods using Boolean satisfiability. Submitted Sept 2005 to the US patent office.
Andrew C. Ling. (2009) Improvements to Field-Programmable Gate Array Logic Synthesis Design Efficiency using Logic Synthesis. Doctor of Philosophy.
Last updated Feb 2010