Adding Large Embedded Blocks (LEBs) to VPR was first proposed by our
project supervisor Professor
Russell Tessier during his sabbatical from the University of Massachusetts.
The goal of this project was to add basic support for non-uniform blocks
in VPR. The non-uniform blocks are representative of RAM or DSP blocks found in commercial
FPGA architectures. As a starting point, we only allowed one type of
non-uniform block in the FPGA architecture specification and
focused on wire-length driven placement and routing where the
wire-length of nets is minimized.
This was a group effort whose members consisted of
Mark Jarvin, Andrew Ling, and Mark
Fang. All members are currently enrolled at the University of Toronto
and are part of the ECE computer group.
Mark Jarvin
is a Masters student under the supervision
of Professor Jianwen Zhu,
Andrew Ling is a Doctorate student under the
supervision of Professor
Stephen Brown and Professor Jianwen Zhu,
and Mark Fang is
a Masters student under supervision of Professor Jonathan
Rose.
Mark Jarvin was responsible for the VPR architecture
specifications to support LEBs. Andrew Ling was responsible for
updating the placer and placer graphics to support LEBs. Andrew also updated
t-vpack to generate
LEB netlists and updated the VPR parser to read them in.
Finally, Mark Fang was responsible for updating the
router for LEB support
Overall, the project was a success where we were able to add
placement support for multi-dimensional LEBs (NxM) and routing support for
multi-height (Nx1)
LEBs. Hopefully, this will provide a good starting point for
other researchers to build upon for heterogeneous FPGA research.
For restricted site
access or questions about VPR LEB support, please contact Andrew Ling (aling AT eecg DOT toronto DOT edu).
Last updated Dec 2005
