University of Toronto Electronics Group Abstracts

Table of All Researchers

Detailed Abstracts for All Researchers

• Adel S Sedra
  Professor
  Direct e-mail to adel@eecg.toronto.edu
  See home page at ~adel
  

  Abstract - Electronic circuit design for analog/digital signal processing. In particular, developing design methods, computer design aids, analysis methods and novel applications for fully-integrated filter networks, and the design and fabrication of high-speed analog circuits. Projects under investigation: current-mode filtering for high-frequency applications; complex-signal filtering for bandpass sigma-delta conversion; computer-aided filter design and synthesis techniques; application of adaptive filtering techniques to on-chip tuning of continuous-time analog filters; Q-enhanced circuit designs employing on-chip inductors for wireless communications; state-space filter synthesis methods. Recent contributions include automatic tuning techniques for continuous-time filters incorporating effects of parasitic elements, a current-mode based circuit technique which enhances the selectivity of integrated inductors and is suitable for operation in the 1 GHz range, the design of a 100 MHz DAC and a high-speed state-space based adaptive analog filter, filter CAD software, filtorX, employed in the design of a complex bandpass sigma-delta convertor.

• Glenn Gulak
  Professor
  Direct e-mail to gulak@eecg.toronto.edu
  See home page at ~gulak
  

  Abstract - VLSI design and applications; VLSI in signal processing and digital communications; parallel algorithms; computer architecture. Projects under investigation include architectures for ML/MAP sequence estimation, logic-enhanced memories for telecommunications and signal processing, ferroelectric memories, field programmable analog arrays. Recent contributions include a field-programmable analog array, fabricated in 1.2-micron CMOS, containing four op-amps, passive components and a transconductor based interconnection network has been used to prototype numerous circuits including a filter biquad, a VCO, a precision rectifier, a signal multiplier and a quadrature oscillator, design and fabrication of CAM-based memory circuits for ATM switch applications.

• Jonathan Rose
  Professor
  Direct e-mail to jayar@eecg.toronto.edu
  See home page at ~jayar
  

  Abstract - Architecture of Field-Programmable Gate Arrays, computer-aided design tools for Field-Programmable Gate Arrays, computer-aided design for VLSI, Field-Programmable Systems. Projects under investigation include high speed field programmable gate arrays (FPGAs), CAD software for FPGAs-logic synthesis and placement, architecture of Field-Reconfigurable Memory, field-programmable systems for fast-prototyping, characterization of circuits and generation of random circuits. Recent contributions include a field-programmable system implementation, a Field-Reconfigurable Memory Implementation, partitioning for multiple FPGAs, architecture of multi-FPGA families.

• David Johns
  Professor
  Direct e-mail to johns@eecg.toronto.edu
  See home page at ~johns
  

  Abstract - Integrated-circuit design for signal processing applications. Projects under investigation include reconfigurable 1-bit filtering on delta-sigma modulated signals, tuning of integrated continuous-time filters, implementation of high-speed analog adaptive filters, analog Viterbi detection for general coding schemes, time-interleaved oversampling A/D converter. Recent contributions include a method for time-interleaving oversampled data converters, a high-speed adaptive pulse shaping filter, a high-speed analog Viterbi detector for partial-response class-IV coded signals.

• david lewis
  Professor
  Direct e-mail to lewis@eecg.toronto.edu

  Abstract - FPGA architecture, Field Programmable Systems, Compute Accelerators, Computer Arithmetic, Digital Filters. Projects under investigation include evaluation of circuit area/speed tradeoff in routing architectures for hierarchical FPGAs, exploration of timing-based placement for improvements in circuit area in hierarchical FPGAs, design of an FPGA architecture targeted at emulation systems, to achieve much better density and utilization using denser coding and a RAM-based implementation, design of a high-speed digital filter operating on oversampled signals, using a highly pipelined architecture to achieve 500MHz in 1.2-micron CMOS. Recent contributions include design and implementation of a logarithmic arithmetic chip for signal processing, achieving 114 MFLOPs in only 16.6 mm**2, offering a factor of 2.6 better performance per unit area than the next best contemporary floating-point unit, design of hardware accelerators for circuit simulation, high speed logic simulation.

• John Long
  Professor
  Direct e-mail to long@eecg.toronto.edu

• Ken Martin
  Professor
  Direct e-mail to martin@eecg.toronto.edu
  See home page at ~martin
  

  Abstract - Analog integrated circuits in CMOS, BiCMOS, and GaAs technologies, fixed and adaptive digital filters for audio applications. Projects under investigation include analog components of wireless communication systems, the design of an analog Viterbi decoder, quadrature high-frequency bipolar oscillator, frequency-domain adaptive digital equalizers for audio applications. Recent contributions include analog high-speed q-enhanced biquads utilising integrated inductors at 1 GHz submitted to BNR for fabrication, complex band-pass oversampling A/D converters for wireless communication systems, a 6 GHz HBT phase-locked loop, a continuous-time BiCMOS low-distortion, high-speed prefilter intended for HDTV, resonator-in-a-loop digital filters (both adaptive and fixed).

• Wai Tung Ng
  Professor
  Direct e-mail to ngwt@eecg.toronto.edu

  Abstract - CMOS/BiCMOS circuits, processing technologies and device design for telecommunications applications, power and RF semiconductor devices for high frequency and power electronics applications. Projects under investigation include advanced BiCMOS device design (RF power transistors and non-volatile memories) for telecommunications, to enhance current CMOS/BiCMOS processes, investigation of merged MOS/bipolar power semiconductor devices that are compatible with modern VLSI processing technology, for smart power IC applications requiring low on-resistance, fast switching speed, high breakdown voltage, and immunity to latch-up. Some recent contributions include development of high voltage and high power semiconductor devices with significant impact on automotive and telecommunication applications.

• Paul Chow
  Professor
  Direct e-mail to pc@eecg.toronto.edu

  Abstract - High-performance microprocessor architectures and memory systems, VLSI architectures, DSP processors, field programmable gate arrays (FPGAs) and systems. Projects under investigation include field-programmable digital/analog array implementation, ATM switch ASIC implementation, DSP processor architecture design, high-performance memory design, architectures for field-programmable systems. Some recent contributions include high-speed FPGA implementations, three-processor cascade Viterbi decoder.

• Stefan Zukotynski
  Professor
  Direct e-mail to zuk@eecg.toronto.edu

• Stephen Alie
  M.A.Sc. Student, Kenneth Martin Supervising
  Direct e-mail to alie@eecg.toronto.edu
  See home page at ~alie
  

  Abstract - My reaserch is on the subject of high speed data-recovery. At the core of the research is a novel phase/frequency detector which is used in a phase-locked loop to perform the critical timing syncrhonization required for data-recovery.

• Amir Hadji-Abdolhamid
  M.A.Sc. Student (Jan. 1997 to Fall 1998), David Johns Supervising
  Direct e-mail to amir@eecg.toronto.edu

• Bryn R. Owen
  Research Associate, Kenneth Martin Supervising
  Direct e-mail to bryn@eecg.toronto.edu
  See home page at ~bryn
  

  Abstract - An analog VLSI layout language called BALLISTIC has been created and is being used to design analog module generators for a variety of useful circuits. These circuits include op amps, comparators, switched-capacitor filters, and digital support circuits. The library will be expanded to include more intricate building-blocks customized for wireless sub-systems. The layout language was made public before its presentation at CICC `95 and is now available to non-profit organizations through both ftp and the world-wide web. To date, it has been used as the layout tool in 10 distinct research projects leading to fabrication.

• Jasmine Cheng
  M.A.Sc. Student (Sep. 1996 to Apr. 1998), David Johns Supervising
  Direct e-mail to chengj@eecg.toronto.edu

• Dean D'Mello
  M.A.Sc. (Completed Fall 1996), Paul Chow & Glenn Gulak Supervising
  Direct e-mail to dmello@eecg.toronto.edu
  See home page at ~dmello
  

• Greg Hartman
  M.A.Sc. Student (Sep. 1995 to Spring 1997), Kenneth Martin Supervising
  Direct e-mail to ghartman@eecg.toronto.edu
  See home page at ~ghartman
  

  Abstract - Continuous Time Adaptive Analog Cable Equalizer

  When transmitting data over copper at rates in the hundreds of Mb/s the attenuation on even a few hundred meters of cable can become significant due to the skin effect and dielectric losses. This attenuation is frequency dependent, making a simple gain stage unsuitable for equalization. Accurate re-generation of the data at these frequencies can be done using a relatively small chip area with low power using an analog filter. To allow proper equalization for an arbitrary cable length an adaptive filter will be designed, fabricated and tested.

• Kapil Kamra
  M.A.Sc. (Completed Summer 1996), David Johns Supervising
  Direct e-mail to kapil@eecg.toronto.edu
  See home page at ~kapil
  

  Abstract - Most adaptive filters used in industry today are digital. The rate of data transmission on a twisted pair copper wire is limited by the inability to equalize the channel at very high frequencies. The objective of this thesis is to investigate the use of analog adaptive filtering in equalizing a high speed twisted pair data communications channel. Speeds of 50 MHz and higher are being targeted. Analog adaptive filtering should be more beneficial than digital adaptive filtering since analog technology often uses less silicon area, consumes less power and attains higher speeds.

• Karen Kozma
  Ph.D. (Completed Fall 1996), David Johns & Adel Sedra Supervising
  Direct e-mail to karen@eecg.toronto.edu
  See home page at ~karen
  

  Abstract - This research addresses various aspects of tuning high-frequency continuous-time filters. It is well known, that the transfer function of continuous-time filters must be tuned over time as the transfer function varies due to fabrication tolerances and environmental changes. The tuning of continuous-time filters in the presence of parasitic poles is being investigated. As well, new approaches for tuning bandpass filters with high quality factors are being explored. Circuits and systems realizing the adaptive tuning of continuous-time filters are also being developed.

• Kasra Ardalan
  M.A.Sc. Student (Sep. 1996 to Fall 1997), David Johns Supervising
  Direct e-mail to kasra@eecg.toronto.edu
  See home page at ~kasra
  

• Khoman Phang
  Ph.D. Student (Fall 1995 to Summer 1999), David Johns Supervising
  Direct e-mail to kphang@eecg.toronto.edu
  See home page at ~kphang
  

  Abstract - I am currently in the midst of defining a research topic. Areas of interest include analog signal processing and adaptive equalization as applied to high-speed wired and wireless communications applications. One possible project would be to investigate the use of analog Viterbi decoders for turbo codes. This research could be applied to the areas of magnetic storage and communications over twisted-pair cable or infrared wireless optical links. The potential benefits would be reduced power consumption and the ability to process higher speed signals over conventional digital processing systems.

• Sebastian Magierowski
  Ph.D. Student (Spring 1997 to Summer 2001), John Long Supervising
  Direct e-mail to magiero@eecg.toronto.edu
  See home page at ~magiero
  

• Marcial K. Chua
  M.A.Sc. Student (Fall 1995 to Spring 1997), Kenneth Martin Supervising
  Direct e-mail to mchua@eecg.toronto.edu
  See home page at ~mchua
  

• Chris Ouslis
  Research Associate, Adel Sedra Supervising
  Direct e-mail to ouslis@eecg.toronto.edu
  See home page at ~filtorx
  

  Abstract - Design, programming, support, and maintenance of the filter-design software filtorX. See associated web pages for more details and ordering information.

• Ralph A I Duncan
  Ph.D. (Completed June 1995), Kenneth Martin & Adel Sedra Supervising
  Direct e-mail to ralph@eecg.toronto.edu

  Abstract - A tunable 1 GHz active-LCR oscillator with on-chip inductors was designed and fabricated for use in front-end demodulation schemes. Additionally, an active-LCR filter based on positive-feedback for on-chip inductor Q-enhancment was designed and fabricated. Both circuits were fabricated in the BATMOS process and later tested.

• Bob Richens
  Lab Technician, Kenneth Martin & David Johns & Adel Sedra Supervising
  Direct e-mail to richens@eecg.toronto.edu
  See home page at ~richens
  

  Abstract - Lab technician for the analogue electronics group, including lab and equipment maintenance, board design and inventory management.

• Sepideh Rezania
  M.A.Sc. (Completed Nov. 1995), Kenneth Martin Supervising
  Direct e-mail to sepideh@eecg.toronto.edu
  See home page at ~sepideh
  

  Abstract - Development of the spreadsheet interface system, PowerDesign, enabled a variety of amplifier circuits to be investigated. The focus was on common-mode feedback circuits, including switched-capacitor and continuous-time implementations. An op amp with the switched-capacitor CMFB circuit was fabricated in the BATMOS process and later tested. Other configurations of the op amp, including single-ended and enhanced-gain, were designed and incorporated into PowerDesign as well.

• Mohammad Hossein Shakiba
  Ph.D. Student (Sep. 1991 to Summer 1997), David Johns & Kenneth Martin Supervising
  Direct e-mail to shakiba@eecg.toronto.edu
  See home page at ~shakiba
  

  Abstract - Analog Viterbi decoders offer the advantages of reduced power and size over digital implementations, primarily due to the elimination of the A/D converter. A new derivation of the Viterbi algorithm for decoding a class-IV partial-response signal is proposed. This algorithm leads to a very simple and fast structure with a complexity much less than that of the A/D converter by itself. A 200 MHz 3.3V class-IV decoder was designed and fabricated in the 0.8um BATMOS process, and experimental results confirm that a speed of 200 MSymbols/s can be achieved with only 30mW power consumption.

• Steve Jantzi
  Ph.D. Student (Sep. 1992 to Summer 1997), Kenneth Martin & Adel Sedra Supervising
  Direct e-mail to steve@eecg.toronto.edu
  See home page at ~steve
  

  Abstract - A 4th-order complex bandpass sigma-delta analog-to-digital converter has been designed and submitted for fabrication in the 0.8um BATMOS process as well as a 0.5um CMOS process. This A/D conversion scheme works directly on the pair of quadrature outputs from the front-end mixer, performing bandpass A/D conversion rather than low-pass conversion, thus reducing image problems and eliminating concerns about self-EMI and 1/f noise. The circuit is designed to clock at 13 MHz (for cellular receivers) and to convert incoming quadrature signals with 4.875 MHz centre frequency and up to 200 kHz (GSM) bandwidth. The converter should realize more than 70dB SNR. Smaller bandwidths can also be converted, such as 100 kHz (CT2+) and 30 kHz (IS-54, AMPS), with SNR increasing for narrower bandwidths.

• Dickson 3.1
  M.A.Sc. Student (Sep. 1996 to Fall 1998), John Long Supervising
  Direct e-mail to tscheung@eecg.toronto.edu

• Wynstan Tong
  M.A.Sc. Student (Jan. 1996 to Oct. 1996), Kenneth Martin Supervising
  Direct e-mail to wynstan@eecg.toronto.edu
  See home page at ~wynstan
  

  Abstract - The design of high-speed analog wireless circuits will be undertaken. Circuits will include frequency synthesizers, phase-locked loops, and operational transconductance amplifiers. Current work is focused on a GHz-range frequency synthesizer that will be incorporated into a digital radio system. The proposed architecture is the fractional-N type. Applications for these circuits include cellular communications, high-speed digital networks and signal-synchronization circuits.

• Rod Zavari
  M.A.Sc. Student (Sep. 1996 to Apr. 1998), David Johns Supervising
  Direct e-mail to zavari@eecg.toronto.edu
  See home page at ~zavari
  

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