Errata  
 
for  
 
Fundamentals of Digital Logic with VHDL Design  

Page 59

 
In problem 2.31, the equation for function f1 should be  

$\parbox{12.5cm}{ \begin{tabbing} f1 $<$= \=(x1 AND x3) OR (NOT x1 AN... ...T x1 AND NOT x3) OR (x2 AND x4) OR\\ \>(NOT x2 AND NOT x4) ;\\ \end{tabbing}}$

Page 179

 
The sixth sentence from the top of the page, which reads:  
 
``These inversions are at inputs $x_1$, $x_5$ and $x_6$, and at the output $f$.''  
 
should be changed to read  
 
``These inversions are at inputs $x_1$, $x_5$, $x_6$, and $x_7$ and at the output $f$.''

Page 248

 
Near the middle of the page, the sentence that reads:  
 
``Similarly, the expressions for $G_2$, $P_2$, $G_3$ and $P_3$ are''  
 
should be changed to read  
 
``Similarly, the expressions for $c_{24}$ and $c_{32}$ are''

Page 304

 
Near the end of Section 6.5 the equation  
 

$${AltB} = \overline{ {AeqB} + {AltB} }$$

 
should be  

$${AltB} = \overline{ {AeqB} + {AgtB} }$$

Page 375

 
In Figure 7.41 the statement:  

$\parbox{12.5cm}{ \begin{tabbing} WAIT UNTIL Clock'EVENT AND Clock = '1' ; \end{tabbing}}$

 
 
should be changed to remove the Clock'EVENT condition:  

$\parbox{12.5cm}{ \begin{tabbing} WAIT UNTIL Clock = '1' ; \end{tabbing}}$

 
Please note that this problem is also present in the sample VHDL code on the CD-ROM provided with the book.

Page 420

   
Figure P7.2 in problem 7.9 is incorrect. The intended figure is:

Page 521

 
In Figure 9.4, the caption for part (a) should be ``Circuit'', not ``State diagram''.

Page 530

 
The $14^{th}$ sentence from the bottom of the page states  
 
``; since we are assuming that $y_2$ changes first,''  
 
This should be changed to  
 
``assuming that $y_1$ changes first in the transition from $y_2y_1 = 01$,''

Page 535

 
There is an error in Example 9.6:  
The circuit in Figure 9.22 is hazardous. If inputs change from r1=r2=0 to r1=r2=1, then depending on gate delays there may be glitches on g1 and g2. The solution is to use a mutual exclusion device (ME) on the input side, which sequences the inputs such that the arbiter circuit never sees both inputs equal to 1.

Page 553

 
In the middle of the page, the sentence  
 
``Of course, this diagram can also be derived directly from Figure 9.39.''  
 
Should be deleted. Figure 9.41 is needed for the derivation, because it shows that D and H are not compatible.

Page 604

 
In Figure 10.12, the caption should refer to the ``control circuit'', not the ``datapath circuit''.

Page 622

 
In Figure 10.28, fourth line from the bottom, the statement:  

$\parbox{12.5cm}{ \begin{tabbing} Sum $<$= R \& R0 + (NOT B +1) ; \end{tabbing}}$

 
 
should be changed to remove the parentheses:  

$\parbox{12.5cm}{ \begin{tabbing} Sum $<$= R \& R0 + NOT B +1 ; \end{tabbing}}$

 
The parentheses cause the VHDL compiler to generate a wrong circuit, because the number of bits in each of the two operands of the addition are not the same. An alternative way to fix this problem is to explicitly sign-extend the $B$ operand:  

$\parbox{12.5cm}{ \begin{tabbing} Sum $<$= R \& R0 + ((B(N$-$1) \& NOT B) +1) ; \end{tabbing}}$

 
Please note that this problem is also present in the sample VHDL code on the CD-ROM provided with the book.