Errata  
 
for the CD-ROM in  
 
Fundamentals of Digital Logic with VHDL Design  

1.

 On the CD-ROM in the VHDL source code file named:  
CDROM-drive: $\backslash$VHDLcode $\backslash$Chap7 $\backslash$Figure7.41 $\backslash$flipflop.vhd the statement:  

$\parbox{12.5cm}{ \begin{tabbing} WAIT UNTIL Clock'EVENT AND Clock = '1' ; \end{tabbing}}$

 
 
should be changed to remove the Clock'EVENT condition:  

$\parbox{12.5cm}{ \begin{tabbing} WAIT UNTIL Clock = '1' ; \end{tabbing}}$

 

2.

 In the VHDL source code file named:  
CDROM-drive: $\backslash$VHDLcode $\backslash$Chap10 $\backslash$Figure10.28 $\backslash$divider.vhd the fourth statement from the bottom is:  

$\parbox{12.5cm}{ \begin{tabbing} Sum $<$ = R \& R0 + (NOT B +1) ; \end{tabbing}}$

 
This statement should be changed to remove the parentheses:  

$\parbox{12.5cm}{ \begin{tabbing} Sum $<$ = R \& R0 + NOT B +1 ; \end{tabbing}}$

 
The parentheses cause the VHDL compiler to generate a wrong circuit, because the number of bits in each of the two operands of the addition are not the same. An alternative way to fix this problem is to explicitly sign-extend the B operand:  

$\parbox{12.5cm}{ \begin{tabbing} Sum $<$ = R \& R0 + ((B(N$-$ 1) \& NOT B) +1) ; \end{tabbing}}$