Placement and Routing for Three-Dimensional FPGAs
Abstract
We explore physical layout for a new three-dimensional (3D) FPGA
architecture. For placement, we introduce a top-down partitioning
technique based on rectilinear Steiner trees. We then employ a
one-step router to produce the final layout. Experimental results
indicate that our approach produces effective 3D layouts, using
considerably shorter average interconnect distance than is achievable
with conventional 2D FPGA's of comparable size.