Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density
Abstract
Field-Programmable Gate Arrays are interesting, general-purpose
computational devices because (1) they have high computational density and
(2) they have fine-grained control of their computational resources since
each gate is independently controlled. The earlier provides them with
a potential 10x advantage in raw peak performance density versus
modern microprocessors. The later can afford a 32x advantage
on random bit-level computations. Nonetheless, typical FPGA usage seldom
extracts this full density advantage. DPGAs are less computationally dense
than FPGAs, but allow most applications to achieve greater, yielded
computational density. The key to unraveling this potential paradox lies
in distinguishing instruction density from active computing density. Since
the storage space for a single instruction is inherently smaller than
the computational element it controls, packing several instructions per
computational unit increases the aggregate instruction capacity of the
device without a significant reduction in computational density.
The number of different instructions executed per computational task often
limits the effective computational density. As a result, DPGAs can
implement many circuits and computing tasks with 3-4x less area than
conventional FPGAs, generally without sacrificing performance.