Stephen Brown's Publications

Most Important Contributions

Books

  1. Stephen D. Brown, and Zvonko Vranesic, "Fundamentals of Digital Logic with Verilog Design, 2nd Edition," McGraw Hill, June, 2007, 900 pages.

  2. Stephen D. Brown, and Zvonko Vranesic, "Fundamentals of Digital Logic with VHDL Design, 2nd Edition," McGraw Hill, July, 2004, 920 pages.

  3. Stephen D. Brown, and Zvonko Vranesic, "Fundamentals of Digital Logic with Verilog Design," McGraw Hill, June, 2002, 850 pages.

  4. Stephen D. Brown, and Zvonko Vranesic, "Fundamentals of Digital Logic with VHDL Design," McGraw Hill, June, 1999, 860 pages.

  5. Stephen D. Brown, Robert J. Francis, Jonathan Rose and Zvonko G. Vranesic, "Field-Programmable Gate Arrays," Springer, 1992, 228 pages.

Journal Papers

  1. Andrew C. Ling, Jianwen Zhu, and Stephen D. Brown, "Scalable Technology Mapping and Clustering Techniques using Decision Diagrams," accepted for publication in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, to appear in Spring 2008

  2. A.C.Ling, D.P.Singh, and Stephen D. Brown, "FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 26, No 7, July 2007, pp. 1196-1210

  3. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Predicting Interconnect Delay for Physical Synthesis in an FPGA CAD Flow", IEEE Transactions on Very Large Scale Integration Systems, Volume 15, Number 8, August 2007, pp. 895-903

  4. Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 25, No. 11, November 2006, pp. 2331-2340.

  5. Andrew C. Ling, Deshanand P. Singh and Stephen D. Brown, "FPGA PLB Evaluation using Quantified Boolean Satisfiability," in IEE Proceedings on Computers and Digital Techniques, Volume 153, Number 3, May 2006, pp. 165-172. ISSN 1350-2387 Invited Journal Paper

  6. Deshanand P. Singh and Stephen D. Brown, "An Area-Efficient Timing Closure Technique for FPGAs using Shannon's Expansion," The Integration, VLSI Journal special issue on VLSI System-On-Chip, pp. 41-50, 2003.

  7. Alireza Kaviani and Stephen D. Brown, "The Hybrid Field-Programmable Architecture," IEEE Design and Test of Computers, April-June 1999, pp. 74-83.

  8. Stephen D. Brown, "FPGA Architectural Research: A Survey," IEEE Design and Test of Computers, Vol. 13, No. 4, 1996, pp. 9-15.

  9. Stephen D. Brown, Muhammad Khellah, and Zvonko Vranesic, "Minimizing FPGA Interconnect Delays," IEEE Design and Test of Computers, Vol. 13, No. 4, 1996, pp. 16-23.

  10. Stephen D. Brown and Jonathan Rose, "FPGA and CPLD Architectures: A Tutorial," IEEE Design and Test of Computers, Vol. 13, No. 2, 1996, pp. 42-57.

  11. Stephen D. Brown, Guy Lemieux, and Muhammad Khellah, "Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays," Journal of VLSI Design, Vol. 4, No. 4, 1996, pp. 275-291.

  12. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol 12, No. 12, Dec. 1993, pp 1827-1838.

  13. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol. 11, No. 5, May 1992, pp. 620-628.

  14. Jonathan Rose and Stephen D. Brown, "Flexibility of Interconnection Structures in Field-Programmable Gate Arrays," IEEE Journal of Solid State Circuits, Vol. 26, No. 3, March 1991, pp. 277-282.

  15. Stephen D. Brown and Zvonko Vranesic, "A Chip for Fault Detection Experiments," Journal of Semi-Custom ICs, Vol. 7, No. 5, 1990, pp. 48-50.

Submitted Journal Papers

  1. Andrew C. Ling, Deshanand Singh, and Stephen D. Brown, Incremental Placement Techniques for FPGAs and Structured ASICs, submitted for consideration to IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Fall 2007

Conference Papers

  1. F. Plavec, Z. G. Vranesic, Stephen D. Brown, "On Digital Search Trees: A Simple Method for Constructing Balanced Binary Trees", in Proceedings of the 2nd International Conference on Software and Data Technologies (ICSOFT '07), vol. 1, Barcelona, Spain, July, 2007, pp. 61-68.

  2. Andrew C. Ling, Deshanand P. Singh, and Stephen D.Brown, "Incremental Placement for Structured ASICs using the Transportation Problem", in Proceedings of the 2007 International Conference of Very Large Scale Integration (VLSI-SoC), Atlanta, Georgia, USA, Oct 2007, pp. 172-177.

  3. Tomasz Czajkowski and Stephen D. Brown, "Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits," proceedings of the 44th Design Automation Conference, San Diego, California, June 4-8, 2007, pp. 324-329.

  4. Andrew Ling, Jianwen Zhu, Stephen D. Brown, "BddCut: Towards Scalable Symbolic Cut Enumeration," in ASP-DAC'07: Proceedings of the 2007 conference on Asia South Pacific Design Automation, Yokohama, Japan, Jan 2007, pp 408-413.

  5. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Mapping Arbitrary Logic Functions into Synchronous Embedded Memories for Area Reduction on FPGAs", Proceedings of the International Conference on Computer-Aided Design, San Jose, California, November 2006, pp. 135-142.

  6. Blair Fort, Davor Capalija, Zvonko G. Vranesic, and Stephen D. Brown, "A Multithreaded Soft Processor for SoPC Area Reduction," in Proceedings of IEEE International Symposium on Custom Computing Machines, Napa, CA, October 2006, pp. 131-142.

  7. Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, "Adaptive FPGAs: High-Level Architecture and a Synthesis Method", In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. 267-274.

  8. Mehrdad Eslami Dehkordi, Stephen D. Brown, Terry Borer, "Modular Partitioning for Incremental Compilation", In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. 113-118.

  9. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, and Stephen D. Brown, "Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow", In Proceedings of the Workshop on System Level Interconnect Prediction, Munich, Germany, March 2006, pp. 3-8.

  10. Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Two-Stage Physical Synthesis for FPGAs", invited double-length paper in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 2005, pp. 171-178.

  11. Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Incremental Retiming for FPGA Physical Synthesis", Proceedings of the 42nd Design Automation Conference (DAC'05), Anaheim, CA, June 2005, pp. 433-438.

  12. Valavan Manohararajah, Deshanand P. Singh, and Stephen D. Brown, "Timing-Driven Functional Decomposition for FPGAs", in Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA, June 2005, pp. 415-422.

  13. A. C. Ling, D. P. Singh, Stephen D. Brown, "FPGA technology mapping: a study of optimality", nominated for best paper in Proceedings of the 42nd Design Automation Conference (DAC05), pp 427-432, Anaheim, CA, June 2005.

  14. Andrew C. Ling, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability", in Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA, June 2005, pp. 399-406.

  15. A.C. Ling, D.P.Singh, and Stephen D. Brown, "FPGA Logic Synthesis using Quantified Boolean Satisfiability", in SAT '05: The 7th International Conference on Theory and Applications of Satisfiability Testing, St. Andrews, Scotland, June 2005, pp. 444-450.

  16. A.C.Ling, D.P.Singh, and Stephen D. Brown, "FPGA PLB Evaluation using Quantified Boolean Satisfiability," Proceedings of Field-Programmable Logic (FPL05), Finland, Aug 2005, pp. 25-29.

  17. Franjo Plavec, Blair Fort, Zvonko Vranesic, and Stephen D. Brown, "Experiences with Soft-Core Processor Design," 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, CO, April 2005, pp. 167-170.

  18. V. Manohararajah, Stephen D. Brown, and Z. Vranesic. "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping". In Proceedings of the International Workshop on Logic and Synthesis, Temecula, California, USA, June 2004, pp. 14-21.

  19. Valavan Manohararajah, Deshanand P. Singh, and Stephen D. Brown, "Post-Placement Functional Decomposition for FPGAs", in Proceedings of the International Workshop on Logic and Synthesis, Temecula, CA, June 2004, pp. 114-118.

  20. Mehrdad Eslami Dehkordi and Stephen D. Brown, "Performance-Driven Recursive Multi-level Clustering," FPT.2003, Tokyo, Japan, December, 2003, pp. 262-269.

  21. Karl Schabas and Stephen D. Brown, "Using Logic Duplication to Improve Performance in FPGAs," FPGA.03, Monterey, CA, February, 2003, pp. 136-142.

  22. Deshanand Singh and Stephen D. Brown, "An Area-Efficient Timing-Closure Technique for FPGAs using Shannon's Expansion," International Conference on VLSI, Las Vegas, NV, February 2003.

  23. Deshanand Singh, Terry Borer, Stephen D. Brown, "Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices," International Conference on VLSI, Las Vegas, NV, February 2003.

  24. Mehrdad Dehkordi and Stephen D. Brown, "The Effect of Cluster Packing and Node Duplication Control in Delay-driven Clustering," FPT.02, Hong Kong, December, 2002, pp. 227-233.

  25. Valavan Manohararajah, Terry Borer, Stephen D. Brown, and Zvonko G. Vranesic, "Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices", in Proceedings of the Conference on Field-Programmable Logic and Applications, Montpelier, France, September 2002, pp. 232-241.

  26. Deshanand Singh and Stephen D. Brown, "Incremental Placement for Layout-Driven Optimizations in FPGAs," ICCAD, San Jose, CA, June. 2002, pp. 752-760.

  27. Deshanand Singh and Stephen D. Brown, "Integrated Retiming and Placement for Field Programmable Gate Arrays," International Symposium on FPGAs (FPGA.2002), Monterey, CA, Feb 2002, pp. 67-76.

  28. Deshanand Singh and Stephen D. Brown, "Constrained Clock Shifting for Field Programmable Gate Arrays," International Symposium on FPGAs (FPGA.2002), Monterey, CA, Feb 2002, pp. 121-126.

  29. Deshanand Singh and Stephen D. Brown, "The Case for Registered Routing Switches in Field Programmable Gate Arrays," International Symposium on FPGAs, Feb 2001, pp. 161-169.

  30. R. Grindley, T. Abdelrahman, Stephen D. Brown, et. al., "The NUMAchine Multiprocessor," International Conference on Parallel Processing, Sept. 2000, pp. 487-496.

  31. Alireza Kaviani and Stephen D. Brown, "Technology Mapping Issues for an FPGA with Lookup Tables and PLA-like blocks," International Symposium on FPGAs, Monterey, California, Feb 2000, pp. 60-66.

  32. Jason Anderson and Stephen D. Brown, "Technology Mapping for Large CPLDs," IEEE Design Automation Conference, San Francisco, June 1998, pp. 698-703.

  33. Alex Grbic, Stephen D. Brown, Steve Caranci, Robin Grindley, Mitch Gusat, Guy Lemieux, Kelvin Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko Vranesic and Zeljko Zilic, "The Design and Implementation of the NUMAchine Multiprocessor," IEEE Design Automation Conference, San Francisco, June 1998, pp. 66-69.

  34. Alireza Kaviani, Daniel Vranesic and Stephen D. Brown, "The Computational FPGA Architecture," IEEE Custom Integrated Circuits Conference, May 1998, Santa Clara, CA, May 1998, pp. 12.2.1-12.2.4.

  35. Jason Anderson and Stephen D. Brown, "An LPGA with Foldable PLA-Style Logic Blocks," FPGA.98, Monterey Bay, CA, February, 1997, pp. 244-252.

  36. Guy G.F. Lemieux, Stephen D. Brown and Daniel Vranesic, "On Two-Step Routing for FPGAs," ISPD, Napa Valley, CA, U.S.A., April 1997, pp 60-66.

  37. Stephen D. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic, and S. Srbljic, "Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools," IEEE Design Automation Conference, Las Vegas, June. 1996, pp. 427-432. This was nominated as a best paper.

  38. Alireza Kaviani and Stephen D. Brown, "Hybrid FPGA Architecture," FPGA.96, Monterey, CA, Feb. 1996, pp. 1-7.

  39. Stephen D. Brown, "An Overview of Technology, Architecture, and CAD Tools for Programmable Logic Devices," IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1994. This was a double-length invited paper, pp. 69-76.

  40. Stephen D. Brown, Muhammad Khellah, and Zvonko Vranesic, "Minimizing FPGA Interconnect Delays," IEEE Custom Integrated Circuits Conference, San Diego CA, May 1994, pp. 181-184.

  41. Muhammad Khellah, Stephen D. Brown, and Zvonko Vranesic, "Modeling Routing Delays in SRAM-based FPGAs," Canadian Conference on VLSI, Nov 1993, pp. 6B.13-6B.18.

  42. Ben Tseng, Jonathan Rose and Stephen D. Brown, "Using Architectural and CAD Interactions to Improve FPGA Routing Architectures," IEEE International Conference on Circuit Design, 1992, 6 pages.

  43. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE International Conference on Computer-Aided Design, Santa Clara, Nov 1990. This publication won a best paper award, pp. 382-385.

  44. Jonathan Rose and Stephen D. Brown, "Flexibility of Interconnection Structures in Field-Programmable Gate Arrays," IEEE Custom Integrated Circuits Conference, Boston, May 1990, pp. 27.5.1-27.5.4.

  45. Stephen D. Brown and Zvonko Vranesic, "A Chip for Fault Detection Experiments," Canadian Conference on VLSI, pp. 9-13, Vancouver, BC, Oct. 1989. This was nominated as a best paper.

Submitted Conference Papers

  1. A.C. Ling, J. Zhu, and Stephen D. Brown, Delay Driven AIG Restructuring using Slack Budget Management, submitted 6 pages to International Great Lakes Symposium on VLSI'08.

  2. A.C. Ling, J. Zhu, and Stephen D. Brown, "Cutting" Congestion with Logic Synthesis, submitted 6 pages to DAC'08.

  3. T.S. Czajkowski and Stephen D. Brown, Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs, submitted for review to the 45th Design Automation Conference, 2008.

  4. F. Plavec, Z. G. Vranesic, Stephen D. Brown, "Automatic Compilation of Streaming Programs into FPGA Hardware", Submitted to the 45th Design Automation Conference (DAC'08), Anaheim, CA, June 2008.