Minimizing FPGA Interconnect Delays
Optimizing FPGA routing architectures for speed performance also
involves improving the CAD tools for mapping circuits. Although their
results are sensitive to the tools used, the authors draw several
basic conclusions about both FPGA routing architectures and CAD tools.
Stephen D. Brown, Muhammad Khellah, and Zvonko Vranesic, "Minimizing FPGA Interconnect Delays," IEEE Design and Test of Computers, Vol. 13, No. 4, 1996, pp. 16-23.
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