FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability
Abstract
This work presents a Field-Programmable Gate Array (FPGA) logic synthesis
technique based upon Boolean
Satisfiability (SAT). This work shows how to map any Boolean function
into an arbitrary PLB architecture without
any custom decomposition techniques. The authors illustrate several
useful applications of this technique by showing
how this technique can be used for architecture evaluation and area
optimization. When evaluating FPGA architecture,
the authors focus on the basic building block of the FPGA which they
refer as a programmable logic block (PLB).
In order to illustrate the flexibility of their evaluation framework,
several unrelated PLB architectures are evaluated
in an automated fashion. Furthermore, the authors show that using
their technique is able to reduce FPGA resource
usage by 27% on average in common subcircuits found in digital design.
Reference
A.C.Ling, D.P.Singh, and Stephen D. Brown, "FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 26, No 7, July 2007, pp. 1196-1210
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