Modeling Routing Delays in SRAM-based FPGAs


This paper presents an efficient technique for estimating the propagation delay of signals in SRAMbased FPGAs, by using an analytic model of MOS integrated circuits. The model provides a facility for experimenting to find the effect that different routing structures in SRAM-based FPGAs have on the speed-performance of implemented circuits. To illustrate the applicability of the technique, two examples of its use are provided.


Muhammad Khellah, Stephen D. Brown, and Zvonko Vranesic, "Modeling Routing Delays in SRAM-based FPGAs," Canadian Conference on VLSI, Nov 1993, pp. 6B.13-6B.18.

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