Two-Stage Physical Synthesis for FPGAs
This paper presents an overview of an industrial physical synthesis
CAD flow for FPGAs. The flow provides a performance speedup of 10%15%
for most circuits, and a significant number of circuits show a speedup
of 20%180%. We describe the algorithms used to achieve this result
including: incremental retiming, BDD-based resynthesis, local rewiring,
and logic replication. The effectiveness of these operations depends on
the ability to accurately determine which portions of logic are timing
critical at a stage of the CAD flow where there is still freedom to
perform logic restructuring. We show how this problem can be effectively
solved by inserting prediction and restrurcturing operations at multiple
points of the FPGA CAD flow.
Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Two-Stage Physical Synthesis for FPGAs", invited double-length paper in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 2005, pp. 171-178.
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