Incremental Retiming for FPGA Physical Synthesis
In this paper, we present a new linear-time retiming algorithm that
produces near-optimal results. Our implementation is specifically
targeted at Altera's Stratix  FPGAbased designs, although the
techniques described are general enough for any implementation medium.
The algorithm is able to handle the architectural constraints of the
target device, multiple timing constraints assigned by the user and
implicit legality constraints. It ensures that register moves do not
create asynchonous problems such as creating a glitch on a clock/reset
Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Incremental Retiming for FPGA Physical Synthesis", Proceedings of the 42nd Design Automation Conference (DAC'05), Anaheim, CA, June 2005, pp. 433-438.
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