A Multithreaded Soft Processor for SoPC Area Reduction
Abstract
The growth in size and performance of Field Programmable
Gate Arrays (FPGAs) has compelled System-on-a-Programmable-Chip (SoPC) designers to use soft processors
for controlling systems with large numbers of intellectual
property (IP) blocks. Soft processors control IP blocks,
which are accessed by the processor either as peripheral devices
or/and by using custom instructions (CIs). In large
systems, chip multiprocessors (CMPs) are used to execute
many programs concurrently. When these programs require
the use of the same IP blocks which are accessed as peripheral
devices, they may have to stall waiting for their turn.
In the case of CIs, the FPGA logic blocks that implement
the CIs may have to be replicated for each processor. In
both of these cases FPGA area is wasted, either by idle soft
processors or the replication of CI logic blocks.
This paper presents a multithreaded (MT) soft processor
for area reduction in SoPC implementations. AnMT processor
allows multiple programs to access the same IP without
the need for the logic replication or the replication of whole
processors. We first designed a single-threaded processor
that is instruction-set compatible to Alteras Nios II soft
processor. Our processor is approximately the same size as
the Nios II Economy version, with equivalent performance.
We augmented our processor to have 4-way interleaved multithreading
capabilities. This paper compares the area usage
and performance of the MT processor versus two CMP
systems, using Alteras and our single-threaded processors,
separately. Our results show that we can achieve an area
savings of about 45% for the processor itself, in addition to
the area savings due to not replicating CI logic blocks.
Reference
Blair Fort, Davor Capalija, Zvonko G. Vranesic, and Stephen D. Brown, "A Multithreaded Soft Processor for SoPC Area Reduction," in Proceedings of IEEE International Symposium on Custom Computing Machines, Napa, CA, October 2006, pp. 131-142.
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