Integrated Retiming and Placement for Field Programmable Gate Arrays
Retiming is a synchronous circuit transformation that can optimize the
delay of a synchronous circuit by moving registers across combinational
circuit elements. The combinational structure remains unchanged and the
observable behavior of the circuit is identical to the original. In
this paper, we address the problem of applying retiming techniques to
circuits implemented in Field Programmable Gate Arrays (FPGAs). FPGAs
contain prefabricated and configurable routing elements that allow us
to easily implement a variety of circuits. However this interconnect
contributes greatly to the overall delay in the implemented circuit. If
a circuit is retimed prior to the placement and routing phases of the
CAD flow, then it has no information about the delays introduced by the
configurable interconnect. Our fundamental experiment is to determine
whether there are any gains in tightly coupling retiming and placement
so that the retiming algorithm has some estimate of the routing delays.
Specifically, we introduce a post-placement retiming algorithm that
understands how to take advantage of FPGA architectural features. This
retiming algorithm may introduce extra registers into the circuit.
These new registers need to be placed in some location in the FPGA.
Retiming register placement is accomplished by a novel incremental
clustering and placement algorithm. The incremental algorithm builds
upon the placement of the non-retimed circuit to intelligently sift
in the newly-introduced registers. In addition, we explore making the
placement algorithms "retiming aware." These placement algorithms try to
place logic blocks in such a way that the subsequent retiming produces
better speed results. These techniques include the identification of
retiming-critical cycles during placement. Our experiments show that
the integration of retiming with placement results in 19% better clock
periods in comparison to the application of retiming before the place
and route steps.
Deshanand Singh and Stephen D. Brown, "Integrated Retiming and Placement for Field Programmable Gate Arrays," International Symposium on FPGAs (FPGA.2002), Monterey, CA, Feb 2002, pp. 67-76.
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