Using Logic Duplication to Improve Performance in FPGAs
Abstract
The purpose of this paper is to introduce a modified packing and
placement algorithm for FPGAs that utilizes logic duplication to improve
performance. The modified packing algorithm was designed to leave
unused basic logic elements (BLEs) in timing critical clusters, to
allow potential targets for logic duplication. The modified placement
algorithm consists of a new stage after placement in which logic
duplication is performed to shorten the length of the critical path. In
this paper, we show that in a representative FPGA architecture using .18
µm technology, the length of the final critical path can be reduced by
an average of 14.1%. Approximately half of this gain comes directly from
the changes to the packing algorithm while the other half comes from the
logic duplication performed during placement.
Reference
Karl Schabas and Stephen D. Brown, "Using Logic Duplication to Improve Performance in FPGAs," FPGA.03, Monterey, CA, February, 2003, pp. 136-142.
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