Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
This paper presents an algorithm for reducing dynamic power
dissipated by Field-Programmable Gate Array (FPGA) circuits.
The algorithm uses a fast probability based model to estimate
glitches on wires in a circuit and then inserts negative edge
triggered FFs at outputs of Lookup Tables (LUTs) that produce
glitches. A negative edge triggered FF maintains the logic value
produced by the LUT in the previous cycle for the first half of the
clock period, filtering glitches that occur at the output of the LUT.
The power dissipation is lowered by reducing the number of
transitions that propagate to the general routing network.
We applied the algorithm to a set of benchmark circuits
implemented on a commercial FPGA, Altera's Stratix II. The
results obtained using Quartus II 5.1 CAD tool show a reduction
in dynamic power dissipation by 7% on average and up to 25%.
Tomasz Czajkowski and Stephen D. Brown, "Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits," proceedings of the 44th Design Automation Conference, San Diego, California, June 4-8, 2007, pp. 324-329.
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