Incremental Placement for Layout-Driven Optimizations in FPGAs
This paper presents an algorithm to update the placement of logic
elements when given an incremental netlist change. Specifically, these
algorithms are targeted to incrementally place logic elements created
by layout-driven circuit restructuring techniques. The incremental
placement engine assumes that the restructuring algorithms provide
a list of new logic elements along with preferred locations for
each of these new elements. It then tries to shift non-critical
logic elements in the original placement out of the way to satisfy
the preferred location requests. Our algorithm considers modern
FPGA architectures with clustered logic blocks that have numerous
architectural constraints. Experiments indicate that our technique
produces results of extremely high quality.
Deshanand Singh and Stephen D. Brown, "Incremental Placement for Layout-Driven Optimizations in FPGAs," ICCAD, San Jose, CA, June. 2002, pp. 752-760.
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