Mapping Arbitrary Logic Functions into Synchronous Embedded Memories for Area Reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies
parts of circuits that can be efficiently mapped into the synchronous
embedded memories found on field programmable gate arrays (FPGAs).
Previous techniques developed for mapping into asynchronous embedded
memories cannot be used because modern FPGAs do not have asynchronous
embedded memories. After technology mapping, an area-prediction cost
function is used to guide the selection of logic cones to be placed
in embedded memories. Extra logic is added to compensate for missing
asynchronous functionality on the synchronous memories. Experiments
conducted on Altera's Stratix device family indicate that this embedded
memory mapping technique can provide an average area reduction of
6.2% and up to 32.5% on a large set of industrial designs. A small
architecture change that increases the size of the FPGA fabric by 0.05%
can increase the average area reduction to 14.1% and up to 59.1% on the
same design set.
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Mapping Arbitrary Logic Functions into Synchronous Embedded Memories for Area Reduction on FPGAs", Proceedings of the International Conference on Computer-Aided Design, San Jose, California, November 2006, pp. 135-142.
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