On Two-Step Routing for FPGAs
We present results which show that a separate global and detailed
routing strategy can be competitive with a combined routing process.
Under restricted architectural assumptions, we compute a
new lower bound for detailed routing and show that our detailed
router typically requires no more than two extra routing tracks
above this computed limit. Also, experimental results show that the
Mapping Anomaly presented in , which suggests that separated
routing may yield arbitrarily poor results in certain instances, is a
concern only if nets are restricted to a single track domain. Finally,
tomotivate future work, we show the latest two-step routing results
that we have achieved with the VPR global router and SEGA detailed
router tools on the largest CBL benchmark circuits.
Guy G.F. Lemieux, Stephen D. Brown and Daniel Vranesic, "On Two-Step Routing for FPGAs," ISPD, Napa Valley, CA, U.S.A., April 1997, pp 60-66.
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