Post-Placement Functional Decomposition for FPGAs


This work explores the effect of adding a simple functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introduced by the new decompositions are resolved by an incremental placement step. Experiments conducted on Alteras Stratix chips indicate that this functional decomposition technique can provide a performance improvement of 7.6% on average, and up to 26.3% on a set of industrial designs.


Valavan Manohararajah, Deshanand P. Singh, and Stephen D. Brown, "Post-Placement Functional Decomposition for FPGAs", in Proceedings of the International Workshop on Logic and Synthesis, Temecula, CA, June 2004, pp. 114-118.

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